Ultrathin (<4 nm) and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits
The outstanding properties of SiO 2, which include high resistivity, excellent dielectric
strength, a large band gap, a high melting point, and a native, low defect density interface …
strength, a large band gap, a high melting point, and a native, low defect density interface …
A review of hot-carrier degradation mechanisms in MOSFETs
A Acovic, G La Rosa, YC Sun - Microelectronics Reliability, 1996 - Elsevier
We review the hot-carrier effects and reliability problem in MOSFET. The mechanisms that
produce the substrate and gate current are discussed, and the various mechanisms for hot …
produce the substrate and gate current are discussed, and the various mechanisms for hot …
Hot-carrier acceleration factors for low power management in DC-AC stressed 40nm NMOS node at high temperature
A Bravaix, C Guérin, V Huard, D Roy… - 2009 IEEE …, 2009 - ieeexplore.ieee.org
Channel hot-carrier degradation presents a renewed interest in the last NMOS nodes where
the device reliability of bulk silicon (core) 40 nm and Input/Output (IO) device is difficult to …
the device reliability of bulk silicon (core) 40 nm and Input/Output (IO) device is difficult to …
Influence of LDD Spacers and H+ Transport on the Total-Ionizing-Dose Response of 65-nm MOSFETs Irradiated to Ultrahigh Doses
The degradation induced by ultrahigh total ionizing dose in 65-nm MOS transistors is
strongly gate-length dependent. The current drive decreases during irradiation, and the …
strongly gate-length dependent. The current drive decreases during irradiation, and the …
[LLIBRE][B] Advanced semiconductor memories: architectures, designs, and applications
AK Sharma - 2009 - dl.acm.org
A valuable reference for the most vital microelectronic components in the marketplace
DRAMs are the technology drivers of high volume semiconductor fabrication processes for …
DRAMs are the technology drivers of high volume semiconductor fabrication processes for …
Investigations on the degradation of 1.2-kV 4H-SiC MOSFETs under repetitive short-circuit tests
X Zhou, H Su, Y Wang, R Yue, G Dai… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
The long-term operational reliability of silicon carbide (SiC) MOSFETs needs to be further
verified before they could replace silicon counterparts in power applications. In this paper …
verified before they could replace silicon counterparts in power applications. In this paper …
A deep insight into the degradation of 1.2-kV 4H-SiC MOSFETs under repetitive unclamped inductive switching stresses
X Zhou, H Su, R Yue, G Dai, J Li… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
In this paper, the long-term reliability of commercial 1.2-kV 4H-SiC MOFSETs under
repetitive unclamped inductive switching stresses is evaluated experimentally. The …
repetitive unclamped inductive switching stresses is evaluated experimentally. The …
Hot-carrier degradation phenomena in lateral and vertical DMOS transistors
P Moens, G Groeseneken - IEEE Transactions on Electron …, 2004 - ieeexplore.ieee.org
The hot-carrier degradation behavior of both a lateral and a vertical integrated DMOS
transistor is investigated in detail by the analysis of the electrical data, charge pum** …
transistor is investigated in detail by the analysis of the electrical data, charge pum** …
Characterization of total safe operating area of lateral DMOS transistors
P Moens, G Van den Bosch - IEEE transactions on device and …, 2006 - ieeexplore.ieee.org
The total safe operating area (SOA) of LDMOS transistors is discussed. It is shown that the
transistors are subjected to different kinds of stresses, yielding a combination of electrical …
transistors are subjected to different kinds of stresses, yielding a combination of electrical …
Effects of bias and temperature on interface-trap annealing in MOS and linear bipolar devices
DM Fleetwood - IEEE Transactions on Nuclear Science, 2022 - ieeexplore.ieee.org
This article reviews the effects of applied bias and temperature on Si/SiO 2 interface-trap
buildup and annealing rates. Electrical and spectroscopic methods are described to …
buildup and annealing rates. Electrical and spectroscopic methods are described to …