[HTML][HTML] Time-to-digital conversion techniques: a survey of recent developments

J Szyduczyński, D Kościelnik, M Miśkowicz - Measurement, 2023 - Elsevier
Time-to-digital converters (TDCs) are key components of time-mode circuits and enablers for
digital processing of analog signals encoded in time. Since design of time-mode circuits …

A 1.9 ps-rms Precision Time-to-Amplitude Converter With 782 fs LSB and 0.79%-rms DNL

G Acconcia, F Malanga, S Farina… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Measuring a time interval in the nanoseconds range has opened the way to 3-D imaging,
where additional information as distance of objects light detection and ranging (LiDAR) or …

A 4.7-ps resolution recirculating cyclic Vernier TDC using DWA-based mismatch correction and a register-based time amplifier

VN Nguyen, JW Lee - IEEE Transactions on Instrumentation …, 2023 - ieeexplore.ieee.org
Herein, we present a recirculating (RC) cyclic Vernier time-to-digital converter (TDC) using
dynamic element matching and a register-based time amplifier (TA). The RC TDC reuses a …

An all-digital low-power, low-frequency GRO-based time to digital converter for biomedical applications

E Zafarkhah, M Zare, NS Anzabi-Nezhad… - … Integrated Circuits and …, 2024 - Springer
In this paper, an all-digital, 10-bit, low-power Time-to-Digital Converter (TDC) is proposed for
use in biomedical applications. To reduce the area and power consumption, as well as …

A 12 ps Precision Two-Step Time-to-Digital Converter Consuming 434 W at 1 MS/s in 180 nm CMOS With a Dual-Slope Time Amplifier

X Xu, Y Wang, Y Zhou, Z Song, B Wu… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
A two-step time-to-digital converter (TDC) is designed for the high-precision time
measurement of the DIRC-like TOF (DTOF) detector at the Super Tau-Charm Facility (STCF) …

A Three-Step Low-Power Multichannel TDC Based on Time Residual Amplifier

F Bouyjou, E Delagnes, F Couderc… - … on Nuclear Science, 2023 - ieeexplore.ieee.org
This article proposes and evaluates an architecture for a low-power time-to-digital converter
(TDC) with high resolution, optimized for high-rate operation (40 MSa/channel), and …

A TDC With Integrated Snapshot Circuit and Calibration in 28-nm CMOS

T Lauber, L Wang, J Bastl, K Vohl… - … on Circuits and …, 2023 - ieeexplore.ieee.org
This brief presents a 135ps dynamic range, 5.45 ps effective resolution 2D Vernier time-to-
digital converter for use in an all-digital phase-locked-loop. The matrix readout array limits …

Design of a high-precision time-to-digital converter in an Elitestek Ti60 field-programmable-gate-array

Z He, X Wen, J Wang, Q Ma, Z Yin - Review of Scientific Instruments, 2024 - pubs.aip.org
The time-to-digital converter (TDC) implemented in a field-programmable-gate-array has
garnered widespread attention due to its flexibility and high-performance capabilities …

A glitch energy reduction method with low complexity dynamic element matching for data converters

W Liu, T Zhang, H Zhang, H Tang… - IEICE Electronics …, 2023 - jstage.jst.go.jp
Due to the appearance of huge glitch while using traditional Dynamic Element Matching
(DEM) in data converters, different kinds of glitch-reduce structures are designed into DEM …

A switch-reduced data weight averaging technique for multi-bit Sigma-Delta modulator

Q Feng, R Yang, L Dong, H Tang… - IEICE Electronics …, 2025 - jstage.jst.go.jp
Due to its simplicity in circuit implementation, conventional Data Weighted Averaging (DWA)
is commonly used to calibrate capacitor mismatch in feedback DACs. However, for low …