Path predicate abstraction for sound system-level models of RT-level circuit designs
J Urdahl, D Stoffel, W Kunz - IEEE Transactions on Computer …, 2014 - ieeexplore.ieee.org
A formal methodology for system verification of system-on-chip (SoC) designs is proposed. It
ensures that system-level models are created that are sound abstractions of the concrete …
ensures that system-level models are created that are sound abstractions of the concrete …
Correct-by-construction design of custom accelerator microarchitectures
Modern application-specific System-on-Chip designs include a variety of accelerator blocks
that customize microcontrollers with domain-specific instruction sets and optimized …
that customize microcontrollers with domain-specific instruction sets and optimized …
Properties first—correct-by-construction RTL design in system-level design flows
This paper presents a new Property-Driven Design (PDD) method that starts from an
abstract system model and integrates formal property checking early into a top-down design …
abstract system model and integrates formal property checking early into a top-down design …
Formal equivalence checking between high-level and RTL hardware designs
Digital applications complexity makes it harder every day to discover and debug behavioral
inconsistencies at register transfer level (RTL). Aiming to bring a solution, several …
inconsistencies at register transfer level (RTL). Aiming to bring a solution, several …
System and methods for generating and managing a virtual device
F **e, K Cong, L Lei - US Patent 8,666,723, 2014 - Google Patents
Certain embodiments of the present invention are configured to permit development and
validation of a device driver or a device application program by using improved virtual …
validation of a device driver or a device application program by using improved virtual …
Equivalence checking for behaviorally synthesized pipelines
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing
hardware designs with acceptable latency and throughput. However, it is a complex …
hardware designs with acceptable latency and throughput. However, it is a complex …
C-to-verilog translation validation
A Leung, D Bounov, S Lerner - 2015 ACM/IEEE International …, 2015 - ieeexplore.ieee.org
To offset the high engineering cost of digital circuit design, hardware engineers are looking
increasingly toward high-level languages such as C and C++ to implement their designs. To …
increasingly toward high-level languages such as C and C++ to implement their designs. To …
Equivalence checking between SLM and RTL using machine learning techniques
J Hu, T Li, S Li - 2016 17th International Symposium on Quality …, 2016 - ieeexplore.ieee.org
The growing complexity of modern digital design makes designers shift toward starting
design exploration using high-level languages, and generating register transfer level (RTL) …
design exploration using high-level languages, and generating register transfer level (RTL) …
System and methods for generating and managing a virtual device
F **e, K Cong, L Lei - US Patent 9,152,540, 2015 - Google Patents
Computer systems, such as Smartphones, personal digital assistants, tablets, netbooks,
laptops, and desktops, typically include a processor, communication unit such as a bus …
laptops, and desktops, typically include a processor, communication unit such as a bus …
Handling design and implementation optimizations in equivalence checking for behavioral synthesis
Behavioral synthesis involves generating hardware design via compilation of its Electronic
System Level (ESL) description to an RTL implementation. Equivalence checking is critical …
System Level (ESL) description to an RTL implementation. Equivalence checking is critical …