[HTML][HTML] Modern computing: Vision and challenges
Over the past six decades, the computing systems field has experienced significant
transformations, profoundly impacting society with transformational developments, such as …
transformations, profoundly impacting society with transformational developments, such as …
Methods for fault tolerance in networks-on-chip
Networks-on-Chip constitute the interconnection architecture of future, massively parallel
multiprocessors that assemble hundreds to thousands of processing cores on a single chip …
multiprocessors that assemble hundreds to thousands of processing cores on a single chip …
Multi-core devices for safety-critical systems: A survey
Multi-core devices are envisioned to support the development of next-generation safety-
critical systems, enabling the on-chip integration of functions of different criticality. This …
critical systems, enabling the on-chip integration of functions of different criticality. This …
A triple core lock-step (tcls) arm® cortex®-r5 processor for safety-critical and ultra-reliable applications
This paper introduces the ARM Triple Core Lock-Step (TCLS) architecture, which builds up
on the industry success of the ARM Cortex-R5 Dual-Core Lock-Step (DCLS) processor …
on the industry success of the ARM Cortex-R5 Dual-Core Lock-Step (DCLS) processor …
Using the case-based ranking methodology for test case prioritization
The test case execution order affects the time at which the objectives of testing are met. If the
objective is fault detection, an inappropriate execution order might reveal most faults late …
objective is fault detection, an inappropriate execution order might reveal most faults late …
EQ-ViT: Algorithm-Hardware Co-Design for End-to-End Acceleration of Real-Time Vision Transformer Inference on Versal ACAP Architecture
While vision transformers (ViTs) have shown consistent progress in computer vision,
deploying them for real-time decision-making scenarios (< 1 ms) is challenging. Current …
deploying them for real-time decision-making scenarios (< 1 ms) is challenging. Current …
Shielding heterogeneous MPSoCs from untrustworthy 3PIPs through security-driven task scheduling
Multiprocessor system-on-chip (MPSoC) platforms face some of the most demanding
security concerns, as they process, store, and communicate sensitive information using third …
security concerns, as they process, store, and communicate sensitive information using third …
The Arm triple core lock-step (TCLS) processor
The Arm Triple Core Lock-Step (TCLS) architecture is the natural evolution of Arm Cortex-R
Dual Core Lock-Step (DCLS) processors to increase dependability, predictability, and …
Dual Core Lock-Step (DCLS) processors to increase dependability, predictability, and …
A survey on fault-tolerant application map** techniques for network-on-chip
N Kadri, M Koudil - Journal of Systems Architecture, 2019 - Elsevier
Reliability is becoming a major concern in Networks-on-Chips (NoCs) design. Several
techniques have been proposed in the literature to deal with different types of faults at …
techniques have been proposed in the literature to deal with different types of faults at …
Exploiting temporal data diversity for detecting safety-critical faults in AV compute systems
Silent data corruption caused by random hardware faults in autonomous vehicle (AV)
computational elements is a significant threat to vehicle safety. Previous research has …
computational elements is a significant threat to vehicle safety. Previous research has …