Multiprocessor architectures and platforms have been introduced to extend the applicability
of Moore's law. They depend on concurrency and synchronization in both software and …

[2]. The Cell Processor from Sony, Toshiba and IBM (STI)[3], and the Sun UltraSPARC T1
(formerly codenamed Niagara)[4] signal the growing popularity of such systems …

As a high performance on-chip communication method, the code division multiple access
(CDMA) technique has recently been applied to networks on chip (NoCs). We propose a …

On-chip interconnects are the performance bottleneck in modern system-on-chips. Code-
division multiple access (CDMA) has been proposed to implement on-chip crossbars due to …

Complexity of designing large and complex NoCs can be reduced/managed by using the
concept of hierarchical networks. In this paper, we propose a methodology for design of …

The Network-on-Chip (NoC) concept has been proposed to replace conventional bus-based
system architectures to create scalable and flexible future SoC designs. A 2D-mesh topology …

Network-on-chip (NoC) structure indicates a capable pattern concept to manage with
growing data transfer needs in digital process. NoC has been come out as a strong aspect …

This paper analyzes the behavior of interconnects in the highly structured environment of a
network-on-chip (NoC). Two distinct classes of wires are considered, namely links between …

Intra-chip communication is a major bottleneck in modern multiprocessor system-on-chip
(MPSoC) designs. The bus topology is the most common on-chip interconnect technology …

Realistic traffic patterns for a multi-processor MPEG-4 architecture are used to evaluate the
performance of network-on-chip (NoC) implementations. In particular, we study the …