11.1 a 1.7 pJ/b 112Gb/s XSR transceiver for intra-package communication in 7nm FinFET technology
R Yousry, E Chen, YM Ying, M Abdullatif… - … Solid-State Circuits …, 2021 - ieeexplore.ieee.org
COVID-19 sparked a paradigm shift for businesses, education, and social life. The measures
taken have emphasized, more than ever, the importance of on-line communication …
taken have emphasized, more than ever, the importance of on-line communication …
A 128-Gb/s 1.3-pJ/b PAM-4 transmitter with reconfigurable 3-tap FFE in 14-nm CMOS
This article describes a 128-Gb/s pulse amplitude-modulation 4-level (PAM-4) transmitter
(TX) implemented in a 14-nm CMOS FinFET technology. Equalization is provided by a fully …
(TX) implemented in a 14-nm CMOS FinFET technology. Equalization is provided by a fully …
30-Gb/s 1.11-pJ/bit single-ended PAM-3 transceiver for high-speed memory links
A 30-Gb/s three-level pulse amplitude modulation (PAM-3) transceiver is designed with a
one-tap tri-level decision feedback equalizer (DFE) to realize a high-speed dynamic random …
one-tap tri-level decision feedback equalizer (DFE) to realize a high-speed dynamic random …
A 36-Gb/s adaptive baud-rate CDR with CTLE and 1-tap DFE in 28-nm CMOS
This letter presents the design details of a 36-Gb/s adaptive baud-rate clock and data
recovery circuit (CDR) with continuous-time linear equalizers and 1-tap decision feedback …
recovery circuit (CDR) with continuous-time linear equalizers and 1-tap decision feedback …
A 56-Gb/s 50-mW NRZ Receiver in 28-nm CMOS
A wireline receiver consisting of a linear equalizer, a decision-feedback equalizer (DFE), a
clock and data recovery (CDR) circuit, and a demultiplexer (DMUX) employs new circuit and …
clock and data recovery (CDR) circuit, and a demultiplexer (DMUX) employs new circuit and …
11.2 A 26.5625-to-106.25 Gb/s XSR SerDes with 1.55 pJ/b Efficiency in 7nm CMOS
R Shivnaraine, M van Ierssel, K Farzan… - … Solid-State Circuits …, 2021 - ieeexplore.ieee.org
The increasing connectivity of devices in our daily lives has driven the need for higher
bandwidth in network and data centers. Recently, we have seen the development of …
bandwidth in network and data centers. Recently, we have seen the development of …
A 2.29 pJ/b 112Gb/s wireline transceiver with RX 4-tap FFE for medium-reach applications in 28nm CMOS
B Ye, K Sheng, W Gai, H Niu, B Zhang… - … Solid-State Circuits …, 2022 - ieeexplore.ieee.org
The increasing demand for higher network data rates by new businesses and entertainment
has never been fulfilled. Mixed-signal PAM-4 transceivers prevail over their ADC-DSP …
has never been fulfilled. Mixed-signal PAM-4 transceivers prevail over their ADC-DSP …
A 1.02-pJ/b 20.83-Gb/s/wire USR transceiver using CNRZ-5 in 16-nm FinFET
An energy-efficient (1.02 pJ/b) and high-speed (20.83 Gb/s/wire, 417 Gb/s/mm) link for ultra-
short reach (USR) applications (up to 6-dB channel loss at the Nyquist frequency of 12.5 …
short reach (USR) applications (up to 6-dB channel loss at the Nyquist frequency of 12.5 …
An ultra-low-jitter, mmW-band frequency synthesizer based on digital subsampling PLL using optimally spaced voltage comparators
This article presents a cascaded architecture of a frequency synthesizer to generate ultra-
low-jitter output signals in a millimeter-wave (mmW) frequency band from 28 to 31 GHz. The …
low-jitter output signals in a millimeter-wave (mmW) frequency band from 28 to 31 GHz. The …
Analog domain carrier phase synchronization in coherent homodyne data center interconnects
Analog domain signal processing is an attractive approach for the reduction of power
consumption in high capacity short reach coherent links. An analog domain equalizer for …
consumption in high capacity short reach coherent links. An analog domain equalizer for …