Single-electron transistor: review in perspective of theory, modelling, design and fabrication
Integrated circuit (IC) technology has grown tremendously over the last few decades. The
prime goal has been to achieve low-power and high-performance in logic and memory …
prime goal has been to achieve low-power and high-performance in logic and memory …
Fabrication of single-electron transistors using field-emission-induced electromigration
W Kume, Y Tomoda, M Hanada… - Journal of Nanoscience …, 2010 - ingentaconnect.com
Fabrication of Single-Electron Transistors Using Field-Emission-Induced Electromigration
Page 1 IP: 5.10.31.211 On: Mon, 10 Jul 2023 19:38:20 Copyright: American Scientific …
Page 1 IP: 5.10.31.211 On: Mon, 10 Jul 2023 19:38:20 Copyright: American Scientific …
Room Temperature Single-Electron Transistor Featuring Gate-Enhanced on -State Current
A Beaumont, C Dubuc, J Beauvais… - IEEE electron device …, 2009 - ieeexplore.ieee.org
A single-electron transistor operating at room temperature was successfully fabricated by an
improved nanodamascene process. It consists in a gated titanium nanowire interspersed by …
improved nanodamascene process. It consists in a gated titanium nanowire interspersed by …
Simulation and design methodology for hybrid SET-CMOS integrated logic at 22-nm room-temperature operation
Single-electron transistor (SET) circuits can be stacked above the CMOS platform to achieve
functional and heterogeneous 3-D integration of nanoelectronic devices. For SET-CMOS …
functional and heterogeneous 3-D integration of nanoelectronic devices. For SET-CMOS …
Spectroscopic ellipsometry on thin titanium oxide layers grown on titanium by plasma oxidation
G Droulers, A Beaumont, J Beauvais… - Journal of Vacuum …, 2011 - pubs.aip.org
Electronic devices based on tunnel junctions require tools able to accurately control the
thickness of thin metal and oxide layers on the order of the nanometer. This article shows …
thickness of thin metal and oxide layers on the order of the nanometer. This article shows …
SET logic driving capability and its enhancement in 3-D integrated SET–CMOS circuit
The driving capability of a single-electron transistor (SET) circuit is sensitive to the load and
interconnects. We discuss about improving the performance of a SET logic in hybrid SET …
interconnects. We discuss about improving the performance of a SET logic in hybrid SET …
SiO2 shallow nanostructures ICP etching using ZEP electroresist
We propose an inductively coupled plasma (ICP) process to etch nanometer scale patterns
defined by electron beam lithography in ZEP520A. The nanoscale patterns have been …
defined by electron beam lithography in ZEP520A. The nanoscale patterns have been …
Inductively coupled plasma etching of amorphous silicon nanostructures over nanotopography using C4F8/SF6 chemistry
Abstract Inductively Coupled Plasma (ICP) etching of amorphous silicon (a-Si)
nanostructures using a continuous C 4 F 8/SF 6 plasma over nanotopography in silicon …
nanostructures using a continuous C 4 F 8/SF 6 plasma over nanotopography in silicon …
Current conduction models in the high temperature single-electron transistor
Single-electron transistor drain current is studied as a function of the temperature. A current
conduction model based on the physical properties of the tunnel junctions is proposed to …
conduction model based on the physical properties of the tunnel junctions is proposed to …
A damascene platform for controlled ultra-thin nanowire fabrication
M Guilmain, T Labbaye, F Dellenbach… - …, 2013 - iopscience.iop.org
This paper presents a damascene process for the fabrication of titanium
micro/nanostructures and nanowires with adjustable thickness down to 2 nm. Their depth is …
micro/nanostructures and nanowires with adjustable thickness down to 2 nm. Their depth is …