Chip floorplanning is the engineering task of designing the physical layout of a computer
chip. Despite five decades of research, chip floorplanning has defied automation, requiring …

Placement for very-large-scale integrated (VLSI) circuits is one of the most important steps
for design closure. This paper proposes a novel GPU-accelerated placement framework …

The Nesterov's method approach to analytic placement has recently demonstrated strong
solution quality and scalability. We dissect the previous implementation strategy and show …

Placement is essential in very large-scale integration (VLSI) physical design, as it directly
affects the design cycle. Despite extensive prior research on placement, achieving fast and …

Macro placement is a critical very large-scale integration (VLSI) physical design problem
that significantly impacts the design power-performance-area (PPA) metrics. This paper …

Placement serves as a fundamental step in VLSI physical design. Recently, GPU-based
global placer DREAMPlace [1] demonstrated its superiority over CPU-based global placers …

Congestion modeling is a key point for improving the routability of VLSI placement solutions.
The underuti-lization of netlist information limits the performance of ex-isting layout-based …

With the dramatic shrink of feature size and the advance of semiconductor technology
nodes, numerous and complicated design rules need to be followed, and a chip design can …

As very large-scale integration technology shrinks to fewer tracks per standard cell, eg, from
10 to 7.5-track libraries (and lesser for 7 nm), there has been a rapid increase in the usage …

Placement is central to IC physical design: it determines spatial embedding, and hence
parasitics and performance. From coarse-to fine-grain, placement is conjointly optimized …