A single-ISA heterogeneous multi-core architecture is achip multiprocessor composed of
cores of varying size, performance, and complexity. This paper demonstrates that …

This paper describes the polymorphous TRIPS architecture which can be configured for
different granularities and types of parallelism. TRIPS contains mechanisms that enable the …

This paper evaluates the Raw microprocessor. Raw addresses thechallenge of building a
general-purpose architecture that performswell on a larger class of stream and embedded …

SIMD organizations amortize the area and power of fetch, decode, and issue logic across
multiple processing units in order to maximize throughput for a given area and power …

Virtual machine (VM) technologies are experiencing a resurgence in both industry and
research communities. VMs offer many desirable features such as security, ease of …

Most implementations of the Single Instruction Multiple Data (SIMD) model available today
require that data elements be packed in vector registers. Operations on disjoint vector …

The vector-thread (VT) architectural paradigm unifies the vectorand multithreaded compute
models. The VT abstraction providesthe programmer with a control processor and a vector of …

Multimedia processing on embedded devices requires an architecture that leads to high
performance, low power consumption, reduced design complexity, and small code size. In …

This paper examines the growing need for a general-purpose ldquoanalytics enginerdquo
that can enable next-generation processing platforms to effectively model events, objects …

A data processing apparatus has a cache and a translation look aside buffer (TLB). A way
table is provided for identifying which of a plurality of cache ways stores require data. Each …