The fabrication of next-generation semiconductor devices has created a need for low-
temperature (≤ 400 C) deposition of highly-conformal (> 95%) SiO 2, SiN x, and SiC films …

Ising machines are annealing processors that can solve combinatorial optimization
problems via the physical evolution of the corresponding Ising graphs. Such machines are …

Applications of deep learning to electronic design automation (EDA) have recently begun to
emerge, although they have mainly been limited to processing of regular structured data …

In the last five decades, the number of transistors on a chip has increased exponentially in
accordance with the Moore's law, and the semiconductor industry has followed this law as …

As minimum feature size and pitch spacing further scale down, triple patterning lithography
is a likely 193 nm extension along the paradigm of double patterning lithography for 14-nm …

As the scale of integrated circuits keeps increasing, it is witnessed that there is a surge in the
research of electronic design automation (EDA) to make the technology node scaling …

In this paper, we survey key design for manufacturing issues for extreme scaling with
emerging nanolithography technologies, including double/multiple patterning lithography …

While double patterning lithography (DPL) has been widely recognized as one of the most
promising solutions for the sub-22nm technology node to enhance pattern printability, triple …

In advanced technology nodes, layout decomposition (LD) and mask optimization (MO) are
two key stages in integrated circuit design. Due to the inconsistency of the objectives of …

TB. Chiou et al.,“Development of layout split algorithms and printability evaluation for double
patterning technology.” Proceed ings of the SPIE, vol. 6924, 2008, pp. 69243M-1-69243M …