Method of constructing a semiconductor device and structure
Z Or-Bach, DC Sekar, B Cronquist, I Beinglass… - US Patent …, 2012 - Google Patents
2011-12-06 Assigned to MONOLITHIC 3D INC. reassignment MONOLITHIC 3D INC.
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
Relax: An architectural framework for software recovery of hardware faults
As technology scales ever further, device unreliability is creating excessive complexity for
hardware to maintain the illusion of perfect operation. In this paper, we consider whether …
hardware to maintain the illusion of perfect operation. In this paper, we consider whether …
Parameter variation tolerance and error resiliency: New design paradigm for the nanoscale era
Variations in process parameters affect the operation of integrated circuits (ICs) and pose a
significant threat to the continued scaling of transistor dimensions. Such parameter …
significant threat to the continued scaling of transistor dimensions. Such parameter …
Multilevel semiconductor device and structure with memory
Z Or-Bach, JW Han - US Patent 10,515,981, 2019 - Google Patents
US10515981B2 - Multilevel semiconductor device and structure with memory - Google
Patents US10515981B2 - Multilevel semiconductor device and structure with memory …
Patents US10515981B2 - Multilevel semiconductor device and structure with memory …
Method of forming three dimensional integrated circuit devices using layer transfer technique
Z Or-Bach, D Sekar, B Cronquist, Z Wurman - US Patent 8,642,416, 2014 - Google Patents
US8642416B2 - Method of forming three dimensional integrated circuit devices using layer
transfer technique - Google Patents US8642416B2 - Method of forming three dimensional …
transfer technique - Google Patents US8642416B2 - Method of forming three dimensional …
Semiconductor device and structure
Z Or-Bach, B Cronquist, I Beinglass, JL De Jong… - US Patent …, 2013 - Google Patents
US8362482B2 - Semiconductor device and structure - Google Patents US8362482B2 -
Semiconductor device and structure - Google Patents Semiconductor device and structure Info …
Semiconductor device and structure - Google Patents Semiconductor device and structure Info …
Toward smart embedded systems: A self-aware system-on-chip (soc) perspective
Embedded systems must address a multitude of potentially conflicting design constraints
such as resiliency, energy, heat, cost, performance, security, etc., all in the face of highly …
such as resiliency, energy, heat, cost, performance, security, etc., all in the face of highly …
Semiconductor device and structure
Z Or-Bach, B Cronquist, I Beinglass, JL De Jong… - US Patent …, 2013 - Google Patents
2011-03-25 Assigned to MONOLITHIC 3D INC. reassignment MONOLITHIC 3D INC.
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
Method for fabrication of a semiconductor device and structure
Z Or-Bach, DC Sekar, B Cronquist - US Patent 8,557,632, 2013 - Google Patents
US8557632B1 - Method for fabrication of a semiconductor device and structure - Google
Patents US8557632B1 - Method for fabrication of a semiconductor device and structure …
Patents US8557632B1 - Method for fabrication of a semiconductor device and structure …
Semiconductor device and structure
Z Or-Bach, B Cronquist, I Beinglass, JL De Jong… - US Patent …, 2013 - Google Patents
2010-12-03 Assigned to NuPGA Corporation reassignment NuPGA Corporation
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …