Approximate computing: An emerging paradigm for energy-efficient design

J Han, M Orshansky - 2013 18th IEEE European Test …, 2013 - ieeexplore.ieee.org
Approximate computing has recently emerged as a promising approach to energy-efficient
design of digital systems. Approximate computing relies on the ability of many systems and …

Exploiting errors for efficiency: A survey from circuits to applications

P Stanley-Marbell, A Alaghi, M Carbin… - ACM Computing …, 2020 - dl.acm.org
When a computational task tolerates a relaxation of its specification or when an algorithm
tolerates the effects of noise in its execution, hardware, system software, and programming …

Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives

R Marculescu, UY Ogras, LS Peh… - … on computer-aided …, 2008 - ieeexplore.ieee.org
To alleviate the complex communication problems that arise as the number of on-chip
components increases, network-on-chip (NoC) architectures have been recently proposed …

New approximate multiplier for low power digital signal processing

F Farshchi, MS Abrishami… - The 17th CSI …, 2013 - ieeexplore.ieee.org
In this paper a low power multiplier is proposed. The proposed multiplier utilizes Broken-
Array Multiplier approximation method on the conventional modified Booth multiplier. This …

The chip is the network: Toward a science of network-on-chip design

R Marculescu, P Bogdan - Foundations and Trends® in …, 2009 - nowpublishers.com
In this survey, we address the concept of network in three different contexts representing the
deterministic, probabilistic, and statistical physics-inspired design paradigms. More …

Fault tolerant parallel filters based on error correction codes

Z Gao, P Reviriego, W Pan, Z Xu… - … Transactions on very …, 2014 - ieeexplore.ieee.org
Digital filters are widely used in signal processing and communication systems. In some
cases, the reliability of those systems is critical, and fault tolerant filter implementations are …

HPR-Mul: An Area and Energy-Efficient High-Precision Redundancy Multiplier by Approximate Computing

J Vafaei, O Akbari - IEEE Transactions on Very Large Scale …, 2024 - ieeexplore.ieee.org
For critical applications that require a higher level of reliability, the triple modular
redundancy (TMR) scheme is usually employed to implement fault-tolerant arithmetic units …

Efficient implementations of reduced precision redundancy (RPR) multiply and accumulate (MAC)

K Chen, L Chen, P Reviriego… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
Multiply and Accumulate (MAC) is one of the most common operations in modern computing
systems. It is for example used in matrix multiplication and in new computational …

Analyzing reduced precision triple modular redundancy under proton irradiation

LA Garcia-Astudillo, L Entrena… - … on Nuclear Science, 2022 - ieeexplore.ieee.org
This work analyzes the performance of the reduced precision redundancy (RPR) error
mitigation technique using the fast Fourier transform (FFT) as a case study. To this purpose …

Characterization of heavy-ion-induced single-event effects in 65 nm bulk CMOS ASIC test chips

CH Chen, P Knag, Z Zhang - IEEE Transactions on Nuclear …, 2014 - ieeexplore.ieee.org
Two 65 nm bulk complementary metal-oxide-semiconductor (CMOS) digital application-
specific integrated circuit (ASIC) chips were designed, and then tested in a heavy ion …