Quo vadis, SLD? Reasoning about the trends and challenges of system level design
A Sangiovanni-Vincentelli - Proceedings of the IEEE, 2007 - ieeexplore.ieee.org
System-level design (SLD) is considered by many as the next frontier in electronic design
automation (EDA). SLD means many things to different people since there is no wide …
automation (EDA). SLD means many things to different people since there is no wide …
A network on chip architecture and design methodology
We propose a packet switched platform for single chip systems which scales well to an
arbitrary number of processor like resources. The platform, which we call Network-on-Chip …
arbitrary number of processor like resources. The platform, which we call Network-on-Chip …
Photonic networks-on-chip for future generations of chip multiprocessors
The design and performance of next-generation chip multiprocessors (CMPs) will be bound
by the limited amount of power that can be dissipated on a single die. We present photonic …
by the limited amount of power that can be dissipated on a single die. We present photonic …
Energy-and performance-aware map** for regular NoC architectures
In this paper, we present an algorithm which automatically maps a given set of intellectual
property onto a generic regular network-on-chip (NoC) architecture and constructs a …
property onto a generic regular network-on-chip (NoC) architecture and constructs a …
[图书][B] Networks on chip
A Jantsch, H Tenhunen - 2003 - Springer
Networks on chip Page 2 NETWORKS ON CHIP Page 3 Networks on Chip edited by Axel
Jantsch Royal Institute of Technology ‚Stockholm and Hannu Tenhunen Royal Institute of …
Jantsch Royal Institute of Technology ‚Stockholm and Hannu Tenhunen Royal Institute of …
Energy-aware map** for tile-based NoC architectures under performance constraints
In this paper, we present an algorithm which automatically maps the IPs/cores onto a
generic regular Network on Chip (NoC) architecture such that the total communication …
generic regular Network on Chip (NoC) architecture such that the total communication …
QNoC: QoS architecture and design process for network on chip
We define Quality of Service (QoS) and cost model for communications in Systems on Chip
(SoC), and derive related Network on Chip (NoC) architecture and design process. SoC …
(SoC), and derive related Network on Chip (NoC) architecture and design process. SoC …
DyAD: smart routing for networks-on-chip
In this paper, we present and evaluate a novel routing scheme called DyAD which combines
the advantages of both deterministic and adaptive routing schemes. More precisely, we …
the advantages of both deterministic and adaptive routing schemes. More precisely, we …
" It's a small world after all": NoC performance optimization via long-range link insertion
Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication
problems. The NoC communication architectures considered so far are based on either …
problems. The NoC communication architectures considered so far are based on either …
Interconnections in multi-core architectures: Understanding mechanisms, overheads and scaling
R Kumar, V Zyuban, DM Tullsen - … International Symposium on …, 2005 - ieeexplore.ieee.org
This paper examines the area, power, performance, and design issues for the on-chip
interconnects on a chip multiprocessor, attempting to present a comprehensive view of a …
interconnects on a chip multiprocessor, attempting to present a comprehensive view of a …