Emerging chips with hundreds and thousands of cores require networks with unprecedented
energy/area efficiency and scalability. To address this, we propose Slim NoC (SN): a new on …

This paper introduces a new, practical routing algorithm, Maze-routing, to tolerate faults in
network-on-chips. The algorithm is the first to provide all of the following properties at the …

Most existing packet-based on-chip networks assume routers have buffers to buffer packets
at times of contention. Recently, deflection-based bufferless routing algorithms have been …

Core systems with network transactions deployed semiconductor materials to develop
wireless networks-on-chip to minimize latency with increased performance. For transmitting …

Network on chip (NoC) has been proposed as an enormously scalable solution to address
communication problems in system on chip (SoC). The interconnections among multiple …

Modern chip multiprocessors (CMPs) employ on-chip networks to enable communication
between the individual cores. Operations such as coherence and synchronization generate …

The continued growth of the computational capability of throughput processors has made
throughput processors the platform of choice for a wide variety of high performance …

As the number of cores scales to tens and hundreds, the energy consumption of routers
across various types of on-chip networks in chip muiltiprocessors (CMPs) increases …

Abstract Network-on-Chip (NoC) has been proposed as an evolving solution for the
scalability and performance demands of the next-generation System-on-Chip (SoC). NoC …

Area and power consumption are the main challenges in Network on Chip (NoC). Indeed,
First Input First Output (FIFO) memory is the key element in NoC. Increasing the FIFO depth …