A survey of network-on-chip security attacks and countermeasures

S Charles, P Mishra - ACM Computing Surveys (CSUR), 2021 - dl.acm.org
With the advances of chip manufacturing technologies, computer architects have been able
to integrate an increasing number of processors and other heterogeneous components on …

Survey of microarchitectural side and covert channels, attacks, and defenses

J Szefer - Journal of Hardware and Systems Security, 2019 - Springer
Over the last two decades, side and covert channel research has shown a variety of ways of
exfiltrating information for a computer system. Processor microarchitectural timing-based …

A survey of microarchitectural timing attacks and countermeasures on contemporary hardware

Q Ge, Y Yarom, D Cock, G Heiser - Journal of Cryptographic Engineering, 2018 - Springer
Microarchitectural timing channels expose hidden hardware states though timing. We survey
recent attacks that exploit microarchitectural features in shared hardware, especially as they …

Invisispec: Making speculative execution invisible in the cache hierarchy

M Yan, J Choi, D Skarlatos, A Morrison… - 2018 51st Annual …, 2018 - ieeexplore.ieee.org
Hardware speculation offers a major surface for micro-architectural covert and side channel
attacks. Unfortunately, defending against speculative execution attacks is challenging. The …

Lord of the ring (s): Side channel attacks on the {CPU}{On-Chip} ring interconnect are practical

R Paccagnella, L Luo, CW Fletcher - 30th USENIX Security Symposium …, 2021 - usenix.org
We introduce the first microarchitectural side channel attacks that leverage contention on the
CPU ring interconnect. There are two challenges that make it uniquely difficult to exploit this …

Random fill cache architecture

F Liu, RB Lee - 2014 47th Annual IEEE/ACM International …, 2014 - ieeexplore.ieee.org
Correctly functioning caches have been shown to leak critical secrets like encryption keys,
through various types of cache side-channel attacks. This nullifies the security provided by …

Evaluation approach for efficient countermeasure techniques against denial-of-service attack on MPSoC-based IoT using multi-criteria decision-making

AAJ Al-Hchaimi, NB Sulaiman, MAB Mustafa… - IEEE …, 2022 - ieeexplore.ieee.org
Context: Denial-of-Service Attack countermeasure techniques (DoS A-CTs) evaluation is a
Multi-criteria decision-making (MCDM) problem based on different MPSoCs of IoT platform …

Are coherence protocol states vulnerable to information leakage?

F Yao, M Doroslovacki… - 2018 IEEE International …, 2018 - ieeexplore.ieee.org
Most commercial multi-core processors incorporate hardware coherence protocols to
support efficient data transfers and updates between their constituent cores. While hardware …

Don't mesh around:{Side-Channel} attacks and mitigations on mesh interconnects

M Dai, R Paccagnella, M Gomez-Garcia… - 31st USENIX Security …, 2022 - usenix.org
This paper studies microarchitectural side-channel attacks and mitigations on the on-chip
mesh interconnect used in modern, server-class Intel processors. We find that, though …

Fort-NoCs: Mitigating the threat of a compromised NoC

DM Ancajas, K Chakraborty, S Roy - Proceedings of the 51st Annual …, 2014 - dl.acm.org
In this paper, we uncover a novel and imminent threat to an emerging computing paradigm:
MPSoCs built with 3rd party IP NoCs. We demonstrate that a compromised NoC (C-NoC) …