Gateway placement for latency and energy efficient data aggregation [wireless sensor networks]

JL Wong, R Jafari, M Potkonjak - 29th Annual IEEE …, 2004 - ieeexplore.ieee.org
We propose the use of multiple gateways to significantly reduce latency and energy
consumption in multi-hop wireless sensor networks during data aggregation. We have …

An improved methodology for resilient design implementation

AB Kahng, S Kang, J Li… - ACM Transactions on …, 2015 - dl.acm.org
Resilient design techniques are used to (i) ensure correct operation under dynamic
variations and to (ii) improve design performance (eg, timing speculation). However …

Slack-aware timing margin redistribution technique utilizing error avoidance flip-flops and time borrowing

M Jayakrishnan, A Chang, JP De Gyvez… - 2015 IFIP/IEEE …, 2015 - ieeexplore.ieee.org
There is much focus on timing error resilience for the speed critical paths of processors. In
the context of growing parameter variations with technology scaling and voltage scaling …

[HTML][HTML] Power and area efficient clock stretching and critical path resha** for error resilience

M Jayakrishnan, A Chang, TTH Kim - Journal of Low Power Electronics …, 2019 - mdpi.com
Energy efficient semiconductor chips are in high demand to cater the needs of today's smart
products. Advanced technology nodes insert high design margins to deal with rising …

Toward Holistic Modeling, Margining and Tolerance of IC Variability

AB Kahng - 2014 IEEE Computer Society Annual Symposium …, 2014 - ieeexplore.ieee.org
The 2013 edition of the International Technology Roadmap for Semiconductors [10]
highlights a slowdown of traditional pitch and density scaling in leading-edge patterning …

Opportunistic design margining for area and power efficient processor pipelines in real time applications

M Jayakrishnan, A Chang, TTH Kim - Journal of Low Power Electronics …, 2018 - mdpi.com
The semiconductor industry is strategically focusing on automotive markets, and significant
investment is targeted to addressing these markets. Runtime better-than-worst-case designs …

SeRA: Self-Repairing Architecture for Dark Silicon Era

H Sriraman, P Venkatasubbu - Journal of Circuits, Systems and …, 2020 - World Scientific
The lifetime reliability of processors has become a major design constraint in the dark silicon
era. Processor reliability issues are mainly due to design defects and aging. Unlike design …

Library pruning and sigma corner libraries for power efficient variation tolerant processor pipelines

M Jayakrishnan, A Chang, T Kim - 2017 IFIP/IEEE International …, 2017 - ieeexplore.ieee.org
Error tolerance techniques are widely used to protect processor pipelines from variation
induced timing errors. In this paper, we propose two standard cell library tuning techniques …

SeRA: Self-Repairing Architecture for Dark Silicon Era.

P Venkatasubbu - Journal of Circuits, Systems & …, 2020 - search.ebscohost.com
The lifetime reliability of processors has become a major design constraint in the dark silicon
era. Processor reliability issues are mainly due to design defects and aging. Unlike design …

[PDF][PDF] A Novel Methodology for Error-Resilient Circuits in Near-Threshold Computing

J Lee - core.ac.uk
The main goal of designing VLSI system is high performance with low energy consumption.
Actually, to realize the human-related techniques, such as internet of things (IoTs) and …