Reduced-complexity min-sum algorithm for decoding LDPC codes with low error-floor

F Angarita, J Valls, V Almenar… - IEEE Transactions on …, 2014‏ - ieeexplore.ieee.org
This paper proposes a low-complexity min-sum algorithm for decoding low-density parity-
check codes. It is an improved version of the single-minimum algorithm where the two …

A reconfigurable LDPC decoder optimized for 802.11 n/ac applications

I Tsatsaragkos, V Paliouras - IEEE Transactions on Very Large …, 2017‏ - ieeexplore.ieee.org
This paper presents a high data-rate low-density parity-check (LDPC) decoder, suitable for
the 802.11 n/ac (WiFi) standard. The innovative features of the proposed decoder relate to …

Algorithm-architecture co-design for domain-specific accelerators in communication and artificial intelligence

Y Tao - 2022‏ - deepblue.lib.umich.edu
The past decade has witnessed an explosive growth of data and the needs for high-speed
data communications and processing. The needs continue to drive the development of new …

LDPC decoding scheduling for faster convergence and lower error floor

HC Lee, YL Ueng - IEEE Transactions on Communications, 2014‏ - ieeexplore.ieee.org
This paper presents a maximum mutual information increase-based algorithm that can be
used to arrange low-density parity-check (LDPC) decoding schedules for faster …

An efficient combined bit-flip** and stochastic LDPC decoder using improved probability tracers

YL Ueng, CY Wang, MR Li - IEEE Transactions on Signal …, 2017‏ - ieeexplore.ieee.org
This paper presents an efficient combined bit-flip** (BF) and stochastic low-density parity-
check decoder, where a BF decoder is used to achieve a reduction in decoding cycles. A …

High-throughput energy-efficient LDPC decoders using differential binary message passing

K Cushon, S Hemati, C Leroux… - IEEE Transactions on …, 2013‏ - ieeexplore.ieee.org
In this paper, we present energy-efficient architectures for decoders of low-density parity
check (LDPC) codes using the differential decoding with binary message passing (DD-BMP) …

Breaking the trap** sets in LDPC codes: Check node removal and collaborative decoding

S Kang, J Moon, J Ha, J Shin - IEEE Transactions on …, 2015‏ - ieeexplore.ieee.org
Trap** sets strongly degrade performance of low-density parity check (LDPC) codes in the
low-error-rate region. This creates significant difficulties for the deployment of LDPC codes …

Error floor analysis of LDPC row layered decoders

A Farsiabi, AH Banihashemi - IEEE Transactions on …, 2021‏ - ieeexplore.ieee.org
In this paper, we analyze the error floor of quasi-cyclic (QC) low-density parity-check (LDPC)
codes decoded by the sum-product algorithm (SPA) with row layered message-passing …

An effective low-complexity error-floor lowering technique for high-rate QC-LDPC codes

HC Lee, PC Chou, YL Ueng - IEEE Communications Letters, 2018‏ - ieeexplore.ieee.org
This letter presents a low-complexity redecoding-based error-floor lowering technique for
quasi-cyclic low-density parity-check codes, where a predetermined set of variable nodes …

Lowering the error floor of LDPC codes using multi-step quantization

S Tolouei, AH Banihashemi - IEEE communications letters, 2013‏ - ieeexplore.ieee.org
A multi-step scheme is proposed for the input quantization of message-passing decoders for
low-density parity-check (LDPC) codes. The proposed scheme, which is applicable to both …