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Ultra-low power VLSI circuit design demystified and explained: A tutorial
In this paper, the state of the art in ultra-low power (ULP) VLSI design is presented within a
unitary framework for the first time. A few general principles are first introduced to gain an …
unitary framework for the first time. A few general principles are first introduced to gain an …
A 32 kb 10T sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS
Ultra-low voltage operation of memory cells has become a topic of much interest due to its
applications in very low energy computing and communications. However, due to parameter …
applications in very low energy computing and communications. However, due to parameter …
Ultralow-voltage process-variation-tolerant Schmitt-trigger-based SRAM design
We analyze Schmitt-Trigger (ST)-based differential-sensing static random access memory
(SRAM) bitcells for ultralow-voltage operation. The ST-based SRAM bitcells address the …
(SRAM) bitcells for ultralow-voltage operation. The ST-based SRAM bitcells address the …
Variation tolerant differential 8T SRAM cell for ultralow power applications
Low power and noise tolerant static random access memory (SRAM) cells are in high
demand today. This paper presents a stable differential SRAM cell that consumes low …
demand today. This paper presents a stable differential SRAM cell that consumes low …
Low store energy, low VDDmin, 8T2R nonvolatile latch and SRAM with vertical-stacked resistive memory (memristor) devices for low power mobile applications
Many mobile SoC chips employ a “two-macro” approach including volatile and nonvolatile
memory macros (ie SRAM and Flash), to achieve high-performance or low-voltage power-on …
memory macros (ie SRAM and Flash), to achieve high-performance or low-voltage power-on …
Energy-efficient subthreshold processor design
Subthreshold circuits have drawn a strong interest in recent ultralow power research. In this
paper, we present a highly efficient subthreshold microprocessor targeting sensor …
paper, we present a highly efficient subthreshold microprocessor targeting sensor …
Single-ended subthreshold SRAM with asymmetrical write/read-assist
In this paper, asymmetrical Write-assist cell virtual ground biasing scheme and positive
feedback sensing keeper schemes are proposed to improve the read static noise margin …
feedback sensing keeper schemes are proposed to improve the read static noise margin …
Yield-driven near-threshold SRAM design
Voltage scaling is desirable in static RAM (SRAM) to reduce energy consumption. However,
commercial SRAM is susceptible to functional failures when V DD is scaled down. Although …
commercial SRAM is susceptible to functional failures when V DD is scaled down. Although …
A variation-tolerant sub-200 mV 6-T subthreshold SRAM
In this paper, we present a deep subthreshold 6-T SRAM, which was fabricated in an
industrial 0.13 mum CMOS technology. We first use detailed simulations to explore the …
industrial 0.13 mum CMOS technology. We first use detailed simulations to explore the …
Nanometer MOSFET variation in minimum energy subthreshold circuits
Minimum energy operation for digital circuits typically requires scaling the power supply
below the device threshold voltage. Advanced technologies offer improved integration …
below the device threshold voltage. Advanced technologies offer improved integration …