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BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining
N Fiege, P Zipf - ACM Transactions on Reconfigurable Technology and …, 2023 - dl.acm.org
Modulo scheduling is the premier technique for throughput maximization of loops in high-
level synthesis by interleaving consecutive loop iterations. The number of clock cycles …
level synthesis by interleaving consecutive loop iterations. The number of clock cycles …
Optimal and heuristic approaches to modulo scheduling with rational initiation intervals in hardware synthesis
A well-known approach for generating custom hardware with high throughput and low
resource usage is modulo scheduling, in which the number of clock cycles between …
resource usage is modulo scheduling, in which the number of clock cycles between …
Fantastic Circuits and Where to Find Them—A Holistic ILP Formulation for Model-Based Hardware Design
N Fiege, P Zipf - ACM Transactions on Reconfigurable Technology and …, 2025 - dl.acm.org
The end of Moore's law and Dennard scaling emphasizes the need for application-specific
computing architectures to achieve high resource and energy efficiency and real-time …
computing architectures to achieve high resource and energy efficiency and real-time …
Integrating energy-optimizing scheduling of moldable streaming tasks with design space exploration for multiple core types on configurable platforms
J Keller, S Litzinger, C Kessler - Journal of Signal Processing Systems, 2022 - Springer
Abstract Design space exploration of a configurable, heterogeneous system for a given
application with required throughput searches for a combination of cores or softcores with …
application with required throughput searches for a combination of cores or softcores with …
SkyCastle: a resource-aware multi-loop scheduler for high-level synthesis
A common optimisation problem in the high-level synthesis (HLS) of FPGA-based
accelerators is to find a microarchitecture that maximises the performance while kee** the …
accelerators is to find a microarchitecture that maximises the performance while kee** the …
Scheduling information-guided efficient high-level synthesis design space exploration
X Qian, J Shi, L Shi, H Zhang, L Bian… - 2022 IEEE 40th …, 2022 - ieeexplore.ieee.org
High-level synthesis (HLS) transforms designs specified by high-level programming
language into RTL designs. In order to get the optimal designs, many design space …
language into RTL designs. In order to get the optimal designs, many design space …
Isomorphic subgraph-based problem reduction for resource minimal modulo scheduling
Modulo scheduling is a powerful method to increase throughput in high-level synthesis for
digital hardware design. When facing large designs, optimal approaches are likely to time …
digital hardware design. When facing large designs, optimal approaches are likely to time …
[PDF][PDF] Advances in ILP-based modulo scheduling for high-level synthesis
J Oppermann - 2019 - tuprints.ulb.tu-darmstadt.de
In today's heterogenous computing world, field-programmable gate arrays (FPGA) represent
the energy-efficient alternative to generic processor cores and graphics accelerators …
the energy-efficient alternative to generic processor cores and graphics accelerators …
Combining design space exploration with task scheduling of moldable streaming tasks on reconfigurable platforms
J Keller, S Litzinger, C Kessler - International Symposium on Applied …, 2021 - Springer
Abstract Design space exploration can be used to find a power-efficient architectural design
for a given application, such as the best suited configuration of a heterogeneous system …
for a given application, such as the best suited configuration of a heterogeneous system …
Efficient Operator Sharing Modulo Scheduling for Sum-Product Network Inference on FPGAs
Probabilistic models are receiving increasing attention as a complementary alternative to
more widespread machine learning approaches such as neural networks. One particularly …
more widespread machine learning approaches such as neural networks. One particularly …