LP-HLS: Automatic power-intent generation for high-level synthesis based hardware implementation flow
The abstraction level for digital designs is rising from Register Transfer Level (RTL) to
algorithmic untimed or transaction-based, followed by an automated high-level synthesis …
algorithmic untimed or transaction-based, followed by an automated high-level synthesis …
Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains
To effectively minimize static power for a wide range of applications, power domains for
coarse-grained reconfigurable array (CGRA) architectures need to be more fine-grained …
coarse-grained reconfigurable array (CGRA) architectures need to be more fine-grained …
Feasibility prediction for rapid IC design space exploration
R Islam - Electronics, 2022 - mdpi.com
The DARPA POSH program echoes with the research community and identifies that
engineering productivity has fallen behind Moore's law, resulting in the prohibitive increase …
engineering productivity has fallen behind Moore's law, resulting in the prohibitive increase …
Design of 2-1 Multiplexer based high-speed, Two-Stage 90 nm Carry Select Adder for fast arithmetic units
This paper proposes a new Two-Stage Carry Select Adder (TSCSA) using a single type of
leaf cell ie, a 2-1 Multiplexer. All the existing Carry Select Adders (CaSeAs) are constructed …
leaf cell ie, a 2-1 Multiplexer. All the existing Carry Select Adders (CaSeAs) are constructed …
Fuzzy c-mean clustering-based decomposition with GA optimizer for FSM synthesis targeting to low power
Y Tao, Y Zhang, Q Wang - Engineering Applications of Artificial Intelligence, 2018 - Elsevier
Reduction on both switching and leakage power has become a research focus in VLSI
design. It makes sense that finite-state machine (FSM) as a main component can contribute …
design. It makes sense that finite-state machine (FSM) as a main component can contribute …
A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block
This paper proposes a novel architecture of excess-1 adder-based Carry Select Adder
(M2CSA) using single leaf cell ie, 2–1 Multiplexer. M2CSA is designed using a new type of …
(M2CSA) using single leaf cell ie, 2–1 Multiplexer. M2CSA is designed using a new type of …
Microcontroller power consumption measurement based on PSoC
SP Janković, VR Drndarević - 2015 23rd Telecommunications …, 2015 - ieeexplore.ieee.org
Microcontrollers are often used as central processing elements in embedded systems.
Because of different sleep and performance modes that microcontrollers support, their …
Because of different sleep and performance modes that microcontrollers support, their …
Development of the science technology engineering and mathematics—Active listening skills assessment (STEM-ALSA)
The purpose of this investigation was to develop the STEM Active Listening Skills
Assessment (STEM-ALSA), a conceptually grounded instrument designed to measure four …
Assessment (STEM-ALSA), a conceptually grounded instrument designed to measure four …
Trade-offs and Optimization: Low Power Approaches for Area, Power Consumption, and Performance in Microprocessor Design
This research paper presents the findings of implementing low-power techniques on RISC V
microprocessors using 90 nm technology. The power consumption of smaller …
microprocessors using 90 nm technology. The power consumption of smaller …
Machine Learning for Power Prediction of ASIC Digital Pre-Distorter Block
G Gondesi - 2024 - diva-portal.org
Background. Application-Specific Integrated Circuits (ASICs), are special circuits made for
specific tasks, often used in telecommunications for handling signals. The Digital Pre …
specific tasks, often used in telecommunications for handling signals. The Digital Pre …