Sustainable modular adaptive redundancy technique emphasizing partial reconfiguration for reduced power consumption
R Al-Haddad, R Oreifej, RA Ashraf… - International Journal of …, 2011 - Wiley Online Library
As reconfigurable devices′ capacities and the complexity of applications that use them
increase, the need for self-reliance of deployed systems becomes increasingly prominent …
increase, the need for self-reliance of deployed systems becomes increasingly prominent …
Power consumption model for partial and dynamic reconfiguration
R Bonamy, D Chillet, S Bilavarn… - … Computing and FPGAs, 2012 - ieeexplore.ieee.org
In the context of embedded systems development, two important challenges are the efficient
use of silicon area and the energy consumption minimization. Hardware accelerated tasks …
use of silicon area and the energy consumption minimization. Hardware accelerated tasks …
Dynamically reconfigurable LTE-compliant OFDM modulator for downlink transmission
ML Ferreira, A Barahimi… - 2016 Conference on …, 2016 - ieeexplore.ieee.org
As the number of wireless devices, services, communication standards and respective
modes of operation rapidly grows, the design of reconfigurable digital baseband processing …
modes of operation rapidly grows, the design of reconfigurable digital baseband processing …
A tiny and multifunctional ICAP controller for dynamic partial reconfiguration system
W Guohua, L Dongming, W Fengzhou… - 2017 NASA/ESA …, 2017 - ieeexplore.ieee.org
As it optimizes the resource utilization of FPGA over time and space, Dynamic Partial
Reconfiguration is an important feature of FPGA. The Internal Configuration Access Port …
Reconfiguration is an important feature of FPGA. The Internal Configuration Access Port …
Power consumption models for the use of dynamic and partial reconfiguration
Minimizing the energy consumption and silicon area are usually two major challenges in the
design of battery-powered embedded computing systems. Dynamic and Partial …
design of battery-powered embedded computing systems. Dynamic and Partial …
Reconfigurable FPGA-based FFT processor for cognitive radio applications
Cognitive Radios (CR) are viewed as a solution for spectrum utilization and management in
next generation wireless networks. In order to adapt themselves to the actual …
next generation wireless networks. In order to adapt themselves to the actual …
Flexible and dynamically reconfigurable FPGA-based FS-FBMC baseband modulator
Filter-bank Multicarrier Modulation (FBMC) is a 5G waveform candidate with improved
spectral efficiency and out-of-band emissions performance compared to OFDM. To address …
spectral efficiency and out-of-band emissions performance compared to OFDM. To address …
[PDF][PDF] Reconfigurable Network-On-Chip (NoC) Architectures for Embedded Systems
S Bayar - 2015 - salihbayar.com
Communication architectures such as Point-to-Point (P2P) and shared bus are poorly
scalable as the number of cores or the communication volume increase. Networkon-Chip …
scalable as the number of cores or the communication volume increase. Networkon-Chip …
A self-reconfigurable platform for general purpose image processing systems on low-cost spartan-6 FPGAs
There is still no partial reconfiguration tool support on low-cost Field Programmable Gate
Arrays (FPGAs) such as old-fashioned Spartan-3 and state-of-the-art Spartan-6 FPGA …
Arrays (FPGAs) such as old-fashioned Spartan-3 and state-of-the-art Spartan-6 FPGA …
Exploiting data-level parallelism for energy-efficient implementation of LDPC decoders and DCT on an FPGA
We explore the use of Data-Level Parallelism (DLP) as a way of improving the energy
efficiency and power consumption involved in running applications on an FPGA. We show …
efficiency and power consumption involved in running applications on an FPGA. We show …