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Prioritising event data over configuration data in a single interface in a SoC/debug architecture
ABT Hopkins - US Patent 9,032,109, 2015 - Google Patents
Roughly described, an integrated circuit chip comprises a plurality of peripheral circuits,
each peripheral circuit con nected to a respective debug unit; a shared hub; and between …
each peripheral circuit con nected to a respective debug unit; a shared hub; and between …
Preventing power gating of a domain
J Ross, RA Shearer, J Tsao - US Patent App. 15/287,578, 2018 - Google Patents
A counter is maintained for power domains that can be powered-off or deactivated. When
this counter is non-zero, the corresponding power domain is not powered-off, even if it is …
this counter is non-zero, the corresponding power domain is not powered-off, even if it is …
System and method to maintain optimal system performance within user defined system level power cap in a changing workload environment
AC Maddukuri, A Muthaiyan, J Gu, E Cho… - US Patent …, 2022 - Google Patents
(57) ABSTRACT A system for controlling power settings is provided that includes a plurality
of components, each component con figured to implement a power control algorithm. A …
of components, each component con figured to implement a power control algorithm. A …
Electronic device and apparatus and method for power management of an electronic device
C Culshaw, GJ Campbell, AJ Gorman… - US Patent …, 2020 - Google Patents
US10860081B2 - Electronic device and apparatus and method for power management of an
electronic device - Google Patents US10860081B2 - Electronic device and apparatus and …
electronic device - Google Patents US10860081B2 - Electronic device and apparatus and …
Adaptive wake-up for power conservation in a processor
P Zhou, N Schlegel, N Ehsan, Z Chen… - US Patent …, 2024 - Google Patents
A processor can include various processing pipelines that perform different data processing
operations, with different pipelines having dedicated logic and memory circuits. A power …
operations, with different pipelines having dedicated logic and memory circuits. A power …
System and method to maintain optimal system performance within user defined system level power cap in a changing workload environment
AC Maddukuri, A Muthaiyan, J Gu, E Cho… - US Patent …, 2024 - Google Patents
A system for controlling power settings is provided that includes a plurality of components,
each component configured to implement a power control algorithm. A controller is coupled …
each component configured to implement a power control algorithm. A controller is coupled …
Peripheral device complying with SDIO standard and method for managing SDIO command
CY Hu - US Patent 9,864,521, 2018 - Google Patents
The invention provides a method of managing SDIO com mands at a host device and a
peripheral device. The host device connected to the peripheral device by a bus compris ing …
peripheral device. The host device connected to the peripheral device by a bus compris ing …
Processor and control method of processor
A Naruse - US Patent 9,626,230, 2017 - Google Patents
(57) ABSTRACT A core executing processes in plural threads specifies one gate to read out
a state of the gate from a thread progress control unit holding information of plural gates …
a state of the gate from a thread progress control unit holding information of plural gates …