Performance comparisons of III–V and strained-Si in planar FETs and nonplanar FinFETs at ultrashort gate length (12 nm)
The exponential miniaturization of Si complementary metal–oxide–semiconductor
technology has been a key to the electronics revolution. However, the downscaling of the …
technology has been a key to the electronics revolution. However, the downscaling of the …
Enhancement of n‐Type Organic Field‐Effect Transistor Performances through Surface Do** with Aminosilanes
N Shin, J Zessin, MH Lee, M Hambsch… - Advanced Functional …, 2018 - Wiley Online Library
Dopants, ie, electronically active impurities, are added to organic semiconductor materials to
control the material's Fermi level and conductivity, to improve injection at the device …
control the material's Fermi level and conductivity, to improve injection at the device …
Insight into conduction band density of states at c-Si/TiO2 interface for efficient heterojunction solar cell
Carrier selective solar cell has become one of the hot spots in the area of Si solar cell. The
proposed architecture FTO/TiO 2/c-Si/ia-Si: H/Cu 2 O/back contact studied through …
proposed architecture FTO/TiO 2/c-Si/ia-Si: H/Cu 2 O/back contact studied through …
Performance analysis of Si nanowire biosensor by numerical modeling for charge sensing
X Yang, WR Frensley, D Zhou… - IEEE Transactions on …, 2011 - ieeexplore.ieee.org
A numerical study on the operation of Si nanowire (NW) biosensors in charge-based
sensing is presented. The simulation is built on physical models that, upon numerical …
sensing is presented. The simulation is built on physical models that, upon numerical …
Electrical characteristic fluctuation of 16-nm-gate high-κ/metal gate bulk FinFET devices in the presence of random interface traps
SC Hsu, Y Li - Nanoscale research letters, 2014 - Springer
In this work, we study the impact of random interface traps (RITs) at the interface of SiO x/Si
on the electrical characteristic of 16-nm-gate high-κ/metal gate (HKMG) bulk fin-type field …
on the electrical characteristic of 16-nm-gate high-κ/metal gate (HKMG) bulk fin-type field …
Observation of 1D behavior in Si nanowires: Toward high-performance TFETs
This article provides experimental evidence of one-dimensional behavior of silicon (Si)
nanowires (NWs) at low-temperature through both transfer (I d–VG) and capacitance …
nanowires (NWs) at low-temperature through both transfer (I d–VG) and capacitance …
Development of a massively parallel nanoelectronic modeling tool and its application to quantum computing devices
SH Lee - 2011 - search.proquest.com
The rapid progress in nanofabrication technologies has led to the possibility of realizing
scalable solid-state quantum computers (QC) which have the potential to outperform …
scalable solid-state quantum computers (QC) which have the potential to outperform …
Investigation of transport, capacitance, and high-accuracy modeling aspects in low-dimensional devices for tunneling applications
R Salazar - 2016 - search.proquest.com
In this work an experimental study has been set out to quantify the impact of quantum
confinement effects on the total gate capacitance of low-dimensional (1D and 2D) Field …
confinement effects on the total gate capacitance of low-dimensional (1D and 2D) Field …
Advanced III-V/Si nano-scale transistors and contacts: Modeling and analysis
SH Park - 2014 - search.proquest.com
The exponential miniaturization of Si CMOS technology has been a key to the electronics
revolution. However, the continuous downscaling of the gate length becomes the biggest …
revolution. However, the continuous downscaling of the gate length becomes the biggest …
[PDF][PDF] DEVELOPMENT OF A MASSIVELY PARALLEL
SH Lee - 2011 - engineering.purdue.edu
Building quantum computers (QC) in silicon has intrigued many researchers around the
world since the proposal of Kane to use the nuclear spin of phosphorus donor as the basic …
world since the proposal of Kane to use the nuclear spin of phosphorus donor as the basic …