A review of III-V Tunnel Field Effect Transistors for future ultra low power digital/analog applications

M Saravanan, E Parthasarathy - Microelectronics Journal, 2021 - Elsevier
Abstract Tunnel Field Effect Transistors (TFETs) have emerged as serious contenders for the
replacement of traditional MOSFET technology for the future ultra low power Analog/Digital …

Simulation study on ferroelectric layer thickness dependence RF/Analog and linearity parameters in ferroelectric tunnel junction TFET

R Saha - Microelectronics Journal, 2021 - Elsevier
In this paper, the impact of ferroelectric layer thickness (t FE) on input drain current
characteristic is reported in ferroelectric tunnel junction (FTJ) TFET through TCAD simulator …

Design and simulation of triple metal double-gate germanium on insulator vertical tunnel field effect transistor

T Chawla, M Khosla, B Raj - Microelectronics journal, 2021 - Elsevier
In this paper, a novel Triple metal double gate germanium on insulator vertical TFET is
proposed and investigated by using SILVACO ATLAS TCAD tool. Gate metal work-function …

Effect of curie temperature on ferroelectric tunnel FET and its RF/analog performance

B Das, B Bhowmick - IEEE Transactions on Ultrasonics …, 2020 - ieeexplore.ieee.org
In this article, a numerical simulation study for the ferroelectric gate oxide tunnel field-effect
transistor (Ferro-TFET) has been presented. The performance of the device is analyzed …

Comparative analysis of noise behavior of highly doped double pocket double-gate and single-gate negative capacitance FET

Malvika, J Talukdar, V Kumar, B Choudhuri… - Journal of Electronic …, 2023 - Springer
This work employs comparative analysis to explore the noise behavior of a single-gate
negative capacitance field-effect transistor (SG-NCFET) and highly doped double pocket …

Design and integration of vertical TFET and memristor for better realization of logical functions

J Singh, S Singh, N Paras - Silicon, 2023 - Springer
This paper deals the hybridization of tunnel FET with the memristor for better execution of
combinational and sequential circuits. Here, device structure of vertical tunnel FET and …

Low frequency noise analysis of single gate extended source tunnel FET

J Talukdar, G Rawat, K Singh, K Mummaneni - Silicon, 2021 - Springer
This paper presents the analysis of noise in Single Gate Extended Source TFET (SG-
ESTFET) considering the absence and presence of interface trap charges, when the device …

Design and analysis of ferro electric-tunneling junction-VTFET for RF/analog and linear application

S Singh - Silicon, 2022 - Springer
In this paper a new ferro material embedded structure is introduced between the tunneling
junction to gain and improve ON/OFF current ratio with steeper subthreshold slope. Various …

Design and simulation-based analysis of triple metal gate with ferroelectric-SiGe heterojunction based vertical TFET for Performance Enhancement

S Singh, R Gupta, Priyanka, R Singh, SK Bhalla - Silicon, 2022 - Springer
In this work, a triple metal gate-ferroelectric material-with SiGe heterojunction based vertical
structure of Tunnel field effect transistor (TMG-FE-SiGe-VTFET) is proposed and …

Analysis of nanoscale digital circuits using novel drain-gate underlap DMG hetero-dielectric TFET

D Gracia, D Nirmal, DJ Moni - Microelectronics Journal, 2022 - Elsevier
In this paper, the investigation of dual metal double gate (DMG) hetero-dielectric TFET with
drain-gate underlap for nanoscale digital applications is analyzed. Drain-gate underlap …