Device, interconnect scaling and interconnection bottleneck are among the major
challenges for CMOS scaling. Furthermore, signal integrity issues like crosstalk-leakage of …

In a typical wireless mesh network (WMN), the interfering links can broadly be classified as
coordinated and non-coordinated links, depending upon the geometric relationship. It is …

Parallel and monolithic three-dimensional (3-D) integration directions realize 3-D integrated
circuits (ICs) by utilizing layer-by-layer implementations, with each functional layer being …

Migration to 3-D provides a possible pathway for future Integrated Circuits (ICs) beyond 2-D
CMOS, which is at the brink of its own fundamental limits. Partial attempts so far for 3-D …

Conventional 2D CMOS technology is reaching fundamental scaling limits, and interconnect
bottleneck is dominating integrated circuit (IC) power and performance. While 3D IC …

Parallel and monolithic 3D-integration directions offer pathways to realize 3D integrated
circuits but still lead to layer-by-layer implementations. This mindset causes challenging …

Hardware implementations of artificial neural networks (ANNs) have become feasible due to
the advent of persistent 2-terminal devices such as memristor, phase change memory, MTJs …

Gate-all-around field effect transistors (FETs) are set to replace FinFETs to enable continued
miniaturization of ICs in the deep nanometer regime. IMEC and IRDS roadmaps project that …

For beyond 2-D CMOS logic, transistor-level 3-D integrations such as monolithic 3-D [1],
Skybridge [2], SN3D [3] hold the most promise. However, such 3-D architectures within small …

At Sub-20nm technologies CMOS scaling faces severe challenges primarily due to
fundamental device scaling limitations, interconnection overhead and complex …