The anticipated end of Moore's law, coupled with the breakdown of Dennard scaling,
compelled everyone to conceive forthcoming computing systems once transistors reach their …

With the end of both Dennard's scaling and Moore's law, computer users and researchers
are aggressively exploring alternative forms of computing in order to continue the …

IMesh, the tile processor architecture's on-chip interconnection network, connects the
multicore processor's tiles with five 2D mesh networks, each specialized for a different use …

Growing transistor counts, limited power budgets, and the breakdown of voltage scaling are
currently conspiring to create a utilization wall that limits the fraction of a chip that can run at …

As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the
scalable fabric for interconnecting the cores. With power now the first-order design …

This paper introduces the Graphite open-source distributed parallel multicore simulator
infrastructure. Graphite is designed from the ground up for exploration of future multi-core …

We expect that many-core microprocessors will push performance per chip from the 10
gigaflop to the 10 teraflop range in the coming decade. To support this increased …

Graphics processors (GPUs) provide a vast number of simple, data-parallel, deeply
multithreaded cores and high memory bandwidths. GPU architectures are becoming …

Buffers in on-chip networks consume significant energy, occupy chip area, and increase
design complexity. In this paper, we make a case for a new approach to designing on-chip …

As multicore architectures enter the mainstream, there is a pressing demand for high-level
programming models that can effectively map to them. Stream programming offers an …