Based on projections of the International Roadmap for Semiconductors (ITRS), the
continued scaling of complementary metal–oxide semiconductor (CMOS) devices will face …

Complex implicit CSG models can be represented hierarchically as a tree of nodes (the
BlobTree). However, current methods cannot be used to visualize changes made to these …

A new hybrid CMOS-nanoscale circuit style has been developed that uses only one type of
Field Effect Transistor (FET) in the logic portions of a design. This is enabled by CMOS …

Nanoscale arrays based on nanowires are expected to have a promising future thanks to
their amazing density and regularity. Experiments demonstrated the feasibility of this …

As silicon CMOS devices are scaled down into the nanoscale regime, new challenges at
both the device and system level are arising. While some of these challenges will be …

Nanoscale computing systems show great potential but at the same time introduce new
challenges not encountered in the world of conventional CMOS designs and manufacturing …

Parameter variations introduced by manufacturing imprecision are becoming more
influential on circuit performance. This is especially the case in emerging nanoscale …

The increasing complexity of hardware features for recent processors makes high
performance code generation very challenging. In particular, several optimization targets …

The design of CAD tools for nanofabrics involves new challenges not encountered with
conventional design flow used for CMOS technology. In this paper, we propose to define a …

In the nanoelectronics era with ever smaller devices and higher densities, power dissipation
and fault tolerance are the two most critical issues to be resolved. The fabrication of reliable …