(57) ABSTRACT A method of forming an array of capacitors and access transistors there-
above comprises forming access transistor trenches partially into insulative material. The …

A method of forming a tier of an array of memory cells within an array area, the memory cells
individually comprising a capacitor and an elevationally-extending transistor, the method …

US10622366B2 - Methods of forming an array comprising pairs of vertically opposed capacitors
and arrays comprising pairs of vertically opposed capacitors - Google Patents US10622366B2 …

A manufacturing method of a semiconductor memory device includes following steps. Bit
line structures and storage node contacts are formed on a semiconductor substrate. A first …

(57) ABSTRACT A method of forming an array comprising pairs of vertically opposed
capacitors comprises forming a conductive lining in individual capacitor openings in …

A wiring structure includes a first conductive pattern includ ing doped polysilicon on a
substrate, an ohmic contact pattern including a metal silicide on the first conductive pattern …

Standard cell circuits employing high aspect ratio voltage rails for reduced resistance are
disclosed. In one aspect, a standard cell circuit is provided that employs a first high aspect …

A method of forming a bit line gate structure of a dynamic random access memory (DRAM)
includes the following steps. A polysilicon layer is formed on a substrate. A sacrificial layer is …

(57) ABSTRACT A wiring structure may include at least two conductive material layers and a
two-dimensional layered material layer in an interface between the at least two conductive …

Semiconductor device may include a landing pad and a lower electrode that is on and is
connected to the landing pad and includes an outer portion and an inner portion inside the …