Go ahead: A partial reconfiguration framework
Exploiting the benefits of partial run-time reconfiguration requires efficient tools. In this
paper, we introduce the tool Go Ahead that is able to implement run-time reconfigurable …
paper, we introduce the tool Go Ahead that is able to implement run-time reconfigurable …
FABulous: An embedded FPGA framework
At the end of CMOS-scaling, the role of architecture design is increasingly gaining
importance. Supporting this trend, customizable embedded FPGAs are an ingredient in …
importance. Supporting this trend, customizable embedded FPGAs are an ingredient in …
Hardware masking, revisited
MaskingHardware masking schemes have shown many advances in the past few years.
Through a series of publications their implementation cost has dropped significantly and …
Through a series of publications their implementation cost has dropped significantly and …
[BOOK][B] FPGAs for software programmers
Dirk Koch · Frank Hannig Daniel Ziener Editors Page 1 Dirk Koch · Frank Hannig Daniel Ziener
Editors FPGAs for Software Programmers Page 2 FPGAs for Software Programmers Page 3 …
Editors FPGAs for Software Programmers Page 2 FPGAs for Software Programmers Page 3 …
The LEAP FPGA operating system
FPGAs offer attractive power and performance for many applications, especially relative to
traditional sequential architectures. In spite of these advantages, FPGAs have been …
traditional sequential architectures. In spite of these advantages, FPGAs have been …
QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlay
The use of FPGAs as compute accelerators has been demonstrated by numerous
researchers as an effective solution to meet the performance requirement across many …
researchers as an effective solution to meet the performance requirement across many …
An efficient ring oscillator PUF using programmable delay units on FPGA
The ring oscillator (RO) PUF can be implemented on different FPGA platforms with high
uniqueness and reliability. To decrease the hardware cost of conventional RO PUFs, a new …
uniqueness and reliability. To decrease the hardware cost of conventional RO PUFs, a new …
An efficient FPGA overlay for portable custom instruction set extensions
D Koch, C Beckhoff… - 2013 23rd international …, 2013 - ieeexplore.ieee.org
Custom instruction set extensions can substantially boost performance of reconfigurable
softcore CPUs. While this approach is commonly tailored to one specific FPGA system, we …
softcore CPUs. While this approach is commonly tailored to one specific FPGA system, we …
FPGA-based protection scheme against hardware trojan horse insertion using dummy logic
Hardware trojan horses (HTH) have recently emerged as a major security threat for field-
programmable gate arrays (FPGAs). Previous studies to protect FPGAs against HTHs may …
programmable gate arrays (FPGAs). Previous studies to protect FPGAs against HTHs may …
PyXEL: an integrated environment for the analysis of fault effects in SRAM-based FPGA routing
In the last decades, FPGAs have been increasingly used in many different mission critical
applications, such as the avionics and aerospace ones. Thus, research interest in studying …
applications, such as the avionics and aerospace ones. Thus, research interest in studying …