Abstract Two-dimensional (2D) semiconductors can potentially be used to create scaled
electronic devices. However, for a number of promising 2D materials—such as black …

In this paper, a detailed 3-D numerical analysis is carried out to study and evaluate CMOS
logic device and circuit performance of gate-all-around (GAA) Si nanowire (NW) field-effect …

This paper explores the effects of changing the device's parameters, such as the gate length
(L g), nanowire radius (r), oxide thickness (t ox), and frequency (f), on the noise …

In this paper, we are proposing a gate oxide stack source halo symmetric and asymmetric
underlap extension nanowire MOSFET with HfO2 spacer at 10 nm regime. The increased …

Vertically stacked nanowire field effect transistors currently dominate the race to become
mainstream devices for 7-nm CMOS technology node. However, these devices are likely to …

The metal-gate granularity-induced threshold voltage (VT) variability and VT mismatch in Si
gate-all-around (GAA) nanowire n-MOSFETs (n-NWFETs) are studied using coupled 3-D …

We have fabricated hybrid channel Ω-gate CMOS nanowires (NWs) with strained SiGe-
channel (cSiGe) p-FETs and Si-channel n-FETs. An optimized process flow based on the Ge …

We have investigated the feasibility of selectively growing SiGe: B layers at 450 C, 20 Torr in
a 300 mm industrial reduced pressure chemical vapor deposition tool. A reduced H 2 carrier …

We have developed an innovative 500 C process for the selective deposition of SiGe: B
Raised Sources and Drains (RSDs). We have first of all studied on blanket Si wafers the in …

This paper presents a novel design and analysis of a low-k source-side asymmetrical spacer
halo-doped nanowire MOSFET. The utilization of high-k spacer materials in MOSFETs …