Adding debug enhancements to assertion checkers for hardware emulation and silicon debug

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Post-silicon validation in the SoC era: A tutorial introduction

P Mishra, R Morad, A Ziv, S Ray - IEEE Design & Test, 2017 - ieeexplore.ieee.org
Editor's note: Post-silicon validation is a complex and critical component of a modern system-
on-chip (SoC) design verification. It includes a large number of inter-related activities each …
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Method of constructing a semiconductor device and structure

Z Or-Bach, DC Sekar, B Cronquist, I Beinglass… - US Patent …, 2012 - Google Patents
2011-12-06 Assigned to MONOLITHIC 3D INC. reassignment MONOLITHIC 3D INC.
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
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Assertion checkers in verification, silicon debug and in-field diagnosis

M Boule, JS Chenard, Z Zilic - 8th International Symposium on …, 2007 - ieeexplore.ieee.org
Assertion based design, and more specifically, assertion based verification (ABV) is quickly
gaining wide acceptance in the design community. Assertions are mainly targeted at …
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Design-for-debug for post-silicon validation: Can high-level descriptions help?

N Nicolici, HF Ko - 2009 IEEE International High Level Design …, 2009 - ieeexplore.ieee.org
Post-silicon validation is an essential step in the design flow, which is needed to
demonstrate that the implemented circuit meets its intended behavior. Due to lack of in …
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Scene classification with semantic fisher vectors

M Dixit, S Chen, D Gao, N Rasiwasia… - Proceedings of the …, 2015 - openaccess.thecvf.com
With the help of a convolutional neural network~(CNN) trained to recognize objects, a scene
image is represented as a bag of semantics (BoS). This involves classifying image patches …
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Multilevel semiconductor device and structure with memory

Z Or-Bach, JW Han - US Patent 10,515,981, 2019 - Google Patents
US10515981B2 - Multilevel semiconductor device and structure with memory - Google
Patents US10515981B2 - Multilevel semiconductor device and structure with memory …
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Method of forming three dimensional integrated circuit devices using layer transfer technique

Z Or-Bach, D Sekar, B Cronquist, Z Wurman - US Patent 8,642,416, 2014 - Google Patents
US8642416B2 - Method of forming three dimensional integrated circuit devices using layer
transfer technique - Google Patents US8642416B2 - Method of forming three dimensional …
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Semiconductor device and structure

Z Or-Bach, B Cronquist, I Beinglass, JL De Jong… - US Patent …, 2013 - Google Patents
US8362482B2 - Semiconductor device and structure - Google Patents US8362482B2 -
Semiconductor device and structure - Google Patents Semiconductor device and structure Info …
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Semiconductor device and structure

Z Or-Bach, B Cronquist, I Beinglass, JL De Jong… - US Patent …, 2013 - Google Patents
2011-03-25 Assigned to MONOLITHIC 3D INC. reassignment MONOLITHIC 3D INC.
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
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Method for fabrication of a semiconductor device and structure

Z Or-Bach, DC Sekar, B Cronquist - US Patent 8,557,632, 2013 - Google Patents
US8557632B1 - Method for fabrication of a semiconductor device and structure - Google
Patents US8557632B1 - Method for fabrication of a semiconductor device and structure …
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