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Reliable on-chip systems in the nano-era: Lessons learnt and future trends
Reliability concerns due to technology scaling have been a major focus of researchers and
designers for several technology nodes. Therefore, many new techniques for enhancing and …
designers for several technology nodes. Therefore, many new techniques for enhancing and …
Variability mitigation in nanometer CMOS integrated systems: A survey of techniques from circuits to software
Variation in performance and power across manufactured parts and their operating
conditions is an accepted reality in modern microelectronic manufacturing processes with …
conditions is an accepted reality in modern microelectronic manufacturing processes with …
Aging-aware logic synthesis
M Ebrahimi, F Oboril, S Kiamehr… - 2013 IEEE/ACM …, 2013 - ieeexplore.ieee.org
As CMOS technology scales down into the nanometer regime, designers have to add
pessimistic timing margins to the circuit as guardbands to avoid timing violations due to …
pessimistic timing margins to the circuit as guardbands to avoid timing violations due to …
SlackProbe: A Flexible and Efficient In Situ Timing Slack Monitoring Methodology
In situ monitoring is an accurate way to monitor circuit delay or timing slack, but usually
incurs significant overhead. We observe that most existing slack monitoring methods focus …
incurs significant overhead. We observe that most existing slack monitoring methods focus …
Aging-and variation-aware delay monitoring using representative critical path selection
F Firouzi, F Ye, K Chakrabarty, MB Tahoori - ACM Transactions on …, 2015 - dl.acm.org
Process together with runtime variations in temperature and voltage, as well as transistor
aging, degrade path delay and may eventually induce circuit failure due to timing variations …
aging, degrade path delay and may eventually induce circuit failure due to timing variations …
A wide-voltage-range half-path timing error-detection system with a 9-transistor transition-detector in 40-nm CMOS
To reduce conservative timing margin in digital circuit designs, adaptive techniques based
on timing-error detection were proposed to monitor the timing of selected critical paths …
on timing-error detection were proposed to monitor the timing of selected critical paths …
Flexibility-aware system-on-polymer (SoP): Concept to prototype
Mechanically flexible, printed, and stretchable electronics are gaining momentum. While
rapid advancement is well underway at the device and circuit levels, researchers have yet to …
rapid advancement is well underway at the device and circuit levels, researchers have yet to …
Synthesis and analysis of design-dependent ring oscillator (DDRO) performance monitors
With CMOS technology scaling, circuit performance has become more sensitive to
manufacturing and environmental variations. Hence, there is a need to measure or monitor …
manufacturing and environmental variations. Hence, there is a need to measure or monitor …
Device aging: A reliability and security concern
D Kraak, M Taouil, S Hamdioui, P Weckx… - 2018 IEEE 23rd …, 2018 - ieeexplore.ieee.org
Device aging is an important concern in nanoscale designs. Due to aging the electrical
behavior of transistors embedded in an integrated circuit deviates from original intended …
behavior of transistors embedded in an integrated circuit deviates from original intended …
Acet: An adaptive clock scheme exploiting comprehensive timing slack for reconfigurable processors
S Ji, W Yang, J Jiang, N **g, W Sheng… - 2023 IEEE 41st …, 2023 - ieeexplore.ieee.org
To ensure the correctness and reliability, digital circuits are designed with conservative
timing margins to accommodate extreme variations in process, voltage, and temperature …
timing margins to accommodate extreme variations in process, voltage, and temperature …