This paper presents an overview for low-power successive approximation register (SAR)
analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and …

The trend of pushing inference from cloud to edge due to concerns of latency, bandwidth,
and privacy has created demand for energy-efficient neural network hardware. This paper …

This article presents an energy-efficient comparator design. The pre-amplifier adopts an
inverter-based input pair powered by a floating reservoir capacitor; it realizes both current …

The need for ultra low-power, area efficient, and high speed analog-to-digital converters is
pushing toward the use of dynamic regenerative comparators to maximize speed and power …

This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits
from technology scaling. It meets extremely low power requirements by using a charge …

A latch-type comparator with a dynamic bias pre-amplifier is implemented in a 65-nm CMOS
process. The dynamic bias with a tail capacitor is simple to implement and ensures that the …

Several classifications exist of Nyquist-rate analog-to-digital converters. In this chapter the
converters are subdivided in parallel search, sequential search, and linear search. Each of …

This paper presents a low offset voltage, low noise dynamic latched comparator using a self-
calibrating technique. The new calibration technique does not require any amplifiers for the …

An ADC for energy scavenging is proposed using a charge-redistribution DAC, a dynamic 2-
stage comparator, and a delay-line-based controller realized in CMOS. The charge …

This article describes a discrete-time zoom analog-to-digital converter (ADC) intended for
audio applications. It uses a coarse 5-bit SAR ADC in tandem with a fine third-order delta …