Post-silicon validation in the SoC era: A tutorial introduction

P Mishra, R Morad, A Ziv, S Ray - IEEE Design & Test, 2017 - ieeexplore.ieee.org
Editor's note: Post-silicon validation is a complex and critical component of a modern system-
on-chip (SoC) design verification. It includes a large number of inter-related activities each …

CAD-Base: An attack vector into the electronics supply chain

K Basu, SM Saeed, C Pilato, M Ashraf… - ACM Transactions on …, 2019 - dl.acm.org
Fabless semiconductor companies design system-on-chips (SoC) by using third-party
intellectual property (IP) cores and fabricate them in offshore, potentially untrustworthy …

Efficient trace signal selection using augmentation and ILP techniques

K Rahmani, P Mishra, S Ray - … international symposium on …, 2014 - ieeexplore.ieee.org
A key problem in post-silicon validation is to identify a small set of traceable signals that are
effective for debug during silicon execution. Most signal selection techniques rely on a …

Postsilicon trace signal selection using machine learning techniques

K Rahmani, S Ray, P Mishra - IEEE Transactions on Very Large …, 2016 - ieeexplore.ieee.org
A key problem in postsilicon validation is to identify a small set of traceable signals that are
effective for debug during silicon execution. Structural analysis used by traditional signal …

Efficient selection of trace and scan signals for post-silicon debug

K Rahmani, S Proch, P Mishra - IEEE Transactions on Very …, 2015 - ieeexplore.ieee.org
Post-silicon validation is a critical part of integrated circuit design methodology. The primary
objective is to detect and eliminate the bugs that have escaped pre-silicon validation phase …

Correctness and security at odds: post-silicon validation of modern SoC designs

S Ray, J Yang, A Basak, S Bhunia - Proceedings of the 52nd Annual …, 2015 - dl.acm.org
We consider the conflicts between requirements from security and post-silicon validation in
SoC designs. Post-silicon validation requires hardware instrumentations to provide …

Scalable trace signal selection using machine learning

K Rahmani, P Mishra, S Ray - 2013 IEEE 31st International …, 2013 - ieeexplore.ieee.org
A key problem in post-silicon validation is to identify a small set of traceable signals that are
effective for debug during silicon execution. Structural analysis used by traditional signal …

Efficient signal selection using fine-grained combination of scan and trace buffers

K Rahmani, P Mishra - … Conference on VLSI Design and 2013 …, 2013 - ieeexplore.ieee.org
Post-silicon validation is a critical part of integrated circuit design methodology. The primary
objective is to detect and eliminate the bugs that has escaped pre-silicon validation phase …

Runtime malware detection using embedded trace buffers

R Elnaggar, K Basu, K Chakrabarty… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
Anti-virus software (AVS) tools are used to detect malware in a system. However, AVS are
vulnerable to attacks. A malicious entity can exploit these vulnerabilities to subvert the AVS …

On multiplexed signal tracing for post-silicon validation

X Liu, Q Xu - IEEE Transactions on Computer-Aided Design of …, 2013 - ieeexplore.ieee.org
Trace-based debug techniques have widely been utilized in the industry to eliminate design
errors escaped from pre-silicon verification. Existing solutions typically trace the same set of …