Local bit line 8T SRAM based in-memory computing architecture for energy-efficient linear error correction codec implementation
Memory reliability is a critical issue in SRAM-based In-Memory Computing (IMC)
architecture. The rapid advance in transistor technology makes SRAM more sensitive to soft …
architecture. The rapid advance in transistor technology makes SRAM more sensitive to soft …
Local bit-line shared pass-gate 8T SRAM based energy efficient and reliable In-Memory Computing architecture
Abstract The In-Memory Computing (IMC) architecture based on Conventional 6T, 8T, and
10T SRAM suffers from compute disturbance, compute-failure, and half-select issues, which …
10T SRAM suffers from compute disturbance, compute-failure, and half-select issues, which …
CiTST-AdderNets: Computing in Toggle Spin Torques MRAM for Energy-Efficient AdderNets
L Luo, E Deng, D Liu, Z Wang, W Huang… - … on Circuits and …, 2023 - ieeexplore.ieee.org
Recently, Adder Neural Networks (AdderNets) have gained widespread attention as an
alternative to traditional Convolutional Neural Networks (CNNs) for deep learning tasks …
alternative to traditional Convolutional Neural Networks (CNNs) for deep learning tasks …
A polymer-based embedded silicon fan-out packaging (P-eSiFO) method for high-density chiplet packaging
L Chen, B Wen, J Du, J Zhang… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Embedded silicon fan-out packaging (eSiFO) features excellent electrical and thermal
performances as well as scalability to 3-D packaging and heterogeneous integration …
performances as well as scalability to 3-D packaging and heterogeneous integration …
MS-SCIM: A Mixed-Signal Stochastic Computing-in-Memory Paradigm for Information Security
Stochastic Computing (SC), an emerging paradigm with advantages in hardware cost and
fault tolerance, is well-suited for applications in image processing and information security …
fault tolerance, is well-suited for applications in image processing and information security …