Challenges and future directions for energy, latency, and lifetime improvements in NVMs
Recently, non-volatile memory (NVM) technology has revolutionized the landscape of
memory systems. With many advantages, such as non volatility and near zero standby …
memory systems. With many advantages, such as non volatility and near zero standby …
Data block manipulation for error rate reduction in STT-MRAM based main memory
Downscaling of semiconductor technology has led DRAM-based main memories to lag
behind emerging non-volatile memories, eg, Spin-Transfer Torque Magnetic Random …
behind emerging non-volatile memories, eg, Spin-Transfer Torque Magnetic Random …
A-CACHE: Alternating cache allocation to conduct higher endurance in NVM-based caches
Recent developments in non-volatile memories (NVMs) have introduced them as an
alternative for SRAMs in on-chip caches. Besides the promising features of NVMs, eg, near …
alternative for SRAMs in on-chip caches. Besides the promising features of NVMs, eg, near …
Towards Sustainable Non-Volatile Memory: Machine Learning and Memory-Aware Data Structures for Energy Efficiency and Longevity
S Kargar - 2024 - search.proquest.com
Non-volatile memory (NVM) technology has revolutionized memory systems with its non-
volatility and near-zero standby power consumption, making it a promising alternative to …
volatility and near-zero standby power consumption, making it a promising alternative to …
Exploiting Non-Volatile Memories to Improve Reliability of Processing Element for Railway Electronic Safety Systems
YS Eom, CS Kim, J Choi - Journal of Electrical Engineering & Technology, 2023 - Springer
The tolerance of soft errors is vital for safety related electronic systems used especially in
railways as defined by EN 50,129. With evolution of fabrication technology, the probability of …
railways as defined by EN 50,129. With evolution of fabrication technology, the probability of …
A survey of low power design techniques for last level caches
E Ofori-Attah, X Wang, MO Agyeman - … 2018, Santorini, Greece, May 2-4 …, 2018 - Springer
The end of Dennard scaling has shifted the focus of performance enhancement in
technology to power budgeting techniques, specifically in the nano-meter domain because …
technology to power budgeting techniques, specifically in the nano-meter domain because …
An Energy-Efficient Cache Architecture for Chip-Multiprocessors Based on Non-Uniformity Accesses
With technology scaling and increasing parallelism levels of new embedded applications,
number of cores in chip-multiprocessors (CMPs) has been shifted from 100 to 1000 cores …
number of cores in chip-multiprocessors (CMPs) has been shifted from 100 to 1000 cores …
A survey of system level power management schemes in the dark-silicon era for many-core architectures
E Ofori-Attah, X Wang… - … on Industrial Networks …, 2018 - pure.northampton.ac.uk
Abstract Power consumption in Complementary Metal Oxide Semiconductor (CMOS)
technology has escalated to a point that only a fractional part of many-core chips can be …
technology has escalated to a point that only a fractional part of many-core chips can be …
Energy-efficient Non Uniform Last Level Caches for Chip-multiprocessors Based on Compression
With technology scaling, the size of cache systems in chip-multiprocessors (CMPs) has been
dramatically increased to efficiently store and manipulate a large amount of data in future …
dramatically increased to efficiently store and manipulate a large amount of data in future …
[PDF][PDF] EFFICIENT AGEING-AWARE TECHNIQUES FOR EMERGING LOW POWER MULTI-CORE SYSTEMS
E OFORI-ATTAH - 2023 - pure.northampton.ac.uk
The rise in power consumption due to the integration of more resources into a single chip
poses a significant threat to performance and resource lifespan in the field of technology. As …
poses a significant threat to performance and resource lifespan in the field of technology. As …