Low Power Standard Logic Gate Cells Design and its Power & Delay Analysis
K Dhanumjaya, MNG Prasad - Journal of Algebraic Statistics, 2022 - publishoa.com
This paper describes the design of a 45nm CMOS technology standard logic library cell for
highly energy-efficient applications of embedded processors. Design of Inverter, NOR and …
highly energy-efficient applications of embedded processors. Design of Inverter, NOR and …
[ZITATION][C] Low Power Logic Gate cell design and its performance analysis
K Dhanumjaya, MNG Prasad - Turkish Journal of Computer and Mathematics …, 2022