This article shows the design of a wideband 3-0 sturdy-multi-stage noise-sha** (SMASH)
continuous-time (CT) incremental delta–sigma (I-) analog-to-digital converter (ADC). The …

This paper presents a high dynamic range (DR) power-efficient voltage-controlled oscillator
(VCO)-based continuous-time ΔΣ modulator. It introduces a robust and low-power fully …

This paper presents a power-efficient single-loop continuous-time (CT) ΔΣ modulator (DSM)
that achieves a SNDR of 90.4 dB over a 2.2 MHz signal bandwidth. The modulator uses a …

We present design techniques for single-bit continuous-time delta–sigma modulators that
attain high resolution (> 16 bits) over a bandwidth (BW) that is more than ten times the audio …

We present design considerations for CTΔΣMs that attempt to achieve high resolution (16+
bits) over a wide bandwidth (> 200 kHz), resulting in a low in-band noise spectral density …

A low-power 113-dB SNR,− 93-dB total harmonic distortion (THD)+ N, digital input-based
filter-less Class-D amplifier for wireless headphone applications is presented. This …

We present a CTΔΣM which uses a virtualground-switched resistor DAC to achieve low
distortion by reducing the effects of inter-symbol interference (/S/), and parasitic resistance in …

This paper presents recent developments in the design of high linearity and dynamic range
digital to analog converters (DAC). It will cover techniques that enable a THD<-120dB and …

The dynamic range (DR) of digital-input closed-loop class-D amplifiers (CDAs) is typically
limited by the noise introduced by their resistive DAC (RDAC) or current-steering DAC …

We describe challenges encountered in the design of continuoustime delta-sigma
modulators that target high resolution (> 16 bits) over wide bandwidths (several hundreds of …