Reducing the multiplicative complexity in logic networks for cryptography and security applications
Reducing the number of AND gates plays a central role in many cryptography and security
applications. We propose a logic synthesis algorithm and tool to minimize the number of …
applications. We propose a logic synthesis algorithm and tool to minimize the number of …
Scalable generic logic synthesis: One approach to rule them all
This paper proposes a novel methodology for multi-level logic synthesis that is independent
from a specific graph data-structure, but formulates synthesis procedures using an abstract …
from a specific graph data-structure, but formulates synthesis procedures using an abstract …
Verilog-to-PyG-A Framework for Graph Learning and Augmentation on RTL Designs
The complexity of modern hardware designs necessitates advanced methodologies for
optimizing and analyzing modern digital systems. In recent times, machine learning (ML) …
optimizing and analyzing modern digital systems. In recent times, machine learning (ML) …
A logic synthesis toolbox for reducing the multiplicative complexity in logic networks
Logic synthesis is a fundamental step in the realization of modern integrated circuits. It has
traditionally been employed for the optimization of CMOS-based designs, as well as for …
traditionally been employed for the optimization of CMOS-based designs, as well as for …
The Role of Multiplicative Complexity in Compiling Low -count Oracle Circuits
We present a constructive method to create quantum circuits that implement oracles| x>| y>|
0> k→| x>| y⊕ f (x)>| 0> k for n-variable Boolean functions f with low T-count. In our method f …
0> k→| x>| y⊕ f (x)>| 0> k for n-variable Boolean functions f with low T-count. In our method f …
Towards finding s-box circuits with optimal multiplicative complexity
In this paper, we present a new method to find S-box circuits with optimal multiplicative
complexity (MC), ie, MC-optimal S-box circuits. We provide new observations for efficiently …
complexity (MC), ie, MC-optimal S-box circuits. We provide new observations for efficiently …
Striving for both quality and speed: Logic synthesis for practical garbled circuits
Garbled circuit (GC) is one of the few promising protocols to realize general-purpose secure
computation. The target computation is represented by a Boolean circuit that is subsequently …
computation. The target computation is represented by a Boolean circuit that is subsequently …
DAG-aware Synthesis Orchestration
Y Li, M Liu, M Ren, A Mishchenko… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
Modern logic synthesis techniques use multilevel technology-independent representations
like and-inverter-graphs (AIGs) for digital logic. This involves structural rewriting …
like and-inverter-graphs (AIGs) for digital logic. This involves structural rewriting …
Expediting Homomorphic Computation via Multiplicative Complexity-aware Multiplicative Depth Minimization
Fully homomorphic encryption (FHE) enables secure data processing without compromising
data access, but its computational cost and slower execution compared to plaintext …
data access, but its computational cost and slower execution compared to plaintext …
Multiplicative complexity of XOR based regular functions
XOR-AND Graphs (XAGs) are an enrichment of the classical AND-Inverter Graphs (AIGs)
with XOR nodes. In particular, XAGs are networks composed by ANDs, XORs, and inverters …
with XOR nodes. In particular, XAGs are networks composed by ANDs, XORs, and inverters …