BilRC: An execution triggered coarse grained reconfigurable architecture

O Atak, A Atalar - IEEE Transactions on Very Large Scale …, 2012 - ieeexplore.ieee.org
We present Bilkent reconfigurable computer (BilRC), a new coarse-grained reconfigurable
architecture (CGRA) employing an execution-triggering mechanism. A control data flow …

Hierarchical design of an application-specific instruction set processor for high-throughput and scalable FFT processing

X Guan, Y Fei, H Lin - IEEE Transactions on Very Large Scale …, 2011 - ieeexplore.ieee.org
Fast Fourier transformation (FFT), a kernel data processing task in communication systems,
has been studied intensively for efficient software and hardware implementations …

Design of an application-specific instruction set processor for high-throughput and scalable FFT

X Guan, H Lin, Y Fei - 2009 Design, Automation & Test in …, 2009 - ieeexplore.ieee.org
Various orthogonal frequency division multiplexing (OFDM)-based wireless communication
standards have raised more stringent requirements on throughput and flexibility of fast …

Design of application specific processors for the cached FFT algorithm

O Atak, A Atalar, E Arikan, H Ishebabi… - … on Acoustics Speech …, 2006 - ieeexplore.ieee.org
Orthogonal frequency division multiplexing (OFDM) is a data transmission technique which
is used in wired and wireless digital communication systems. In this technique, fast Fourier …

[PDF][PDF] Comparison of ASIP and Standard Microprocessor based Navigation Processors

G Kappen, L Kurz, TG Noll - Chair of Electrical Engineering and Computer …, 2007 - Citeseer
Tobias G. NOLL received the Ing.(grad.) degree in Electrical Engineering from the
Fachhochschule Koblenz in 1974, the Dipl.-Ing. degree in Electrical Engineering from the …

A hierarchical design of an application-specific instruction set processor for high-throughput FFT

X Guan, Y Fei, H Lin - 2009 IEEE International Symposium on …, 2009 - ieeexplore.ieee.org
This paper presents a novel hierarchical design of an application-specific instruction set
processor (ASIP) tailored for fast Fourier transformation (FFT), a kernel data transformation …

System-level synthesis of multi-ASIP platforms using an uncertainty model

L Micconi, J Madsen, P Pop - INTEGRATION, the VLSI journal, 2015 - Elsevier
In this paper we propose a system-level synthesis for MPSoCs that integrates multiple
Application Specific Instruction Set Processors (ASIPs). Each ASIP is customized for a …

[PDF][PDF] Efficient cached 64 point FFT processor using floating point arithmetic for OFDM application

C Padma, P Jagadamba, RR Patil - Instrumentation, Mesure …, 2022 - researchgate.net
Accepted: 9 February 2022 Presently Fourth generation and other wireless systems are
focused area for the research and development in the communication field. Fast Fourier …

[책][B] Multi-objective Application-specific Instruction set Processor Design: Towards High Performance, Energy-efficient, and Secure Embedded Systems

H Lin - 2011 - search.proquest.com
Abstract Application-Specific Instruction set Processor (ASIP) has become an increasingly
popular platform for embedded systems because of its high performance, great flexibility …

A Probabilistic Approach for the System-Level Design of Multi-ASIP Platforms

L Micconi - 2015 - orbit.dtu.dk
Abstract Application Specific Instruction-set Processors (ASIPs) offer a good trade off
between performance and flexibility when compared to general purpose processors or …