Rapid progress in CMOS technology since the late 1990s has increased the vulnerability of
processors toward faults. Subsequently, the focus of computer architects has shifted toward …

We present here a report produced by a workshop on 'Addressing failures in exascale
computing'held in Park City, Utah, 4–11 August 2012. The charter of this workshop was to …

Architecture Design for Soft Errors provides a comprehensive description of the architectural
techniques to tackle the soft error problem. It covers the new methodologies for quantitative …

With continued CMOS scaling, future shipped hardware will be increasingly vulnerable to in-
the-field faults. To be broadly deployable, the hardware reliability solution must incur low …

High availability is an increasingly important requirement for enterprise systems, often
valued more than performance. Systems designed for high availability typically use …

Transactional Memory (TM) simplifies parallel programming by allowing for parallel
execution of atomic tasks. Thus far, TM systems have focused on implementing transactional …

The huge investment in the design and production of multicore processors may be put at risk
because the emerging highly miniaturized but unreliable fabrication technologies will …

In the near future, hardware is expected to become increasingly vulnerable to faults due to
continuously decreasing feature size. Software-level symptoms have previously been used …

Continued technology scaling is resulting in systems with billions of devices. Unfortunately,
these devices are prone to failures from various sources, resulting in even commodity …

As silicon process technology scales deeper into the nanometer regime, hardware defects
are becoming more common. Such defects are bound to hinder the correct operation of …