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Force-directed scheduling for the behavioral synthesis of ASICs
PG Paulin, JP Knight - … on Computer-Aided Design of Integrated …, 2002 - ieeexplore.ieee.org
A general scheduling methodology is presented that can be integrated into specialized or
general-purpose high-level synthesis systems. An initial version of the force-directed …
general-purpose high-level synthesis systems. An initial version of the force-directed …
[KNIHA][B] Electronic design automation: synthesis, verification, and test
This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI
practitioners and researchers in need of fluency in an" adjacent" field will find this an …
practitioners and researchers in need of fluency in an" adjacent" field will find this an …
The high-level synthesis of digital systems
MC McFarland, AC Parker… - Proceedings of the …, 1990 - ieeexplore.ieee.org
High-level synthesis systems start with an abstract behavioral specification of a digital
system and find a register-transfer level structure that realizes the given behavior. The …
system and find a register-transfer level structure that realizes the given behavior. The …
A formal approach to the scheduling problem in high level synthesis
CT Hwang, JH Lee, YC Hsu - IEEE Transactions on Computer …, 1991 - ieeexplore.ieee.org
An integer linear programming (ILP) model for the scheduling problem in high-level
synthesis is presented. In addition to time-constrained scheduling and resource-constrained …
synthesis is presented. In addition to time-constrained scheduling and resource-constrained …
Force-directed scheduling in automatic data path synthesis
PG Paulin, JP Knight - Proceedings of the 24th ACM/IEEE Design …, 1987 - dl.acm.org
The HAL system performs data path synthesis using a new scheduling algorithm that is part
of an interdependent scheduling and allocation scheme. This scheme uses an estimate of …
of an interdependent scheduling and allocation scheme. This scheme uses an estimate of …
Data path allocation based on bipartite weighted matching
CY Huang, YS Chen, YL Lin, YC Hsu - … of the 27th ACM/IEEE Design …, 1991 - dl.acm.org
We propose a graph-theoretic approach for the data path allocation problem. We
decompose the problem into three subproblems:(1) register allocation,(2) operation …
decompose the problem into three subproblems:(1) register allocation,(2) operation …
[KNIHA][B] Processor description languages
Efficient design of embedded processors plays a critical role in embedded systems design.
Processor description languages and their associated specification, exploration and rapid …
Processor description languages and their associated specification, exploration and rapid …
A dynamic and reliability-driven scheduling algorithm for parallel real-time jobs executing on heterogeneous clusters
In this paper, a heuristic dynamic scheduling scheme for parallel real-time jobs executing on
a heterogeneous cluster is presented. In our system model, parallel real-time jobs, which are …
a heterogeneous cluster is presented. In our system model, parallel real-time jobs, which are …
On the design of fault-tolerant scheduling strategies using primary-backup approach for computational grids with low replication costs
Fault-tolerant scheduling is an imperative step for large-scale computational grid systems,
as often geographically distributed nodes co-operate to execute a task. By and large …
as often geographically distributed nodes co-operate to execute a task. By and large …
Retargetable code generation based on structural processor description
Abstract Design automation for embedded systems comprising both hardware and software
components demands for code generators integrated into electronic CAD systems. These …
components demands for code generators integrated into electronic CAD systems. These …