Force-directed scheduling for the behavioral synthesis of ASICs

PG Paulin, JP Knight - … on Computer-Aided Design of Integrated …, 2002 - ieeexplore.ieee.org
A general scheduling methodology is presented that can be integrated into specialized or
general-purpose high-level synthesis systems. An initial version of the force-directed …

[KNIHA][B] Electronic design automation: synthesis, verification, and test

LT Wang, YW Chang, KTT Cheng - 2009 - books.google.com
This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI
practitioners and researchers in need of fluency in an" adjacent" field will find this an …

The high-level synthesis of digital systems

MC McFarland, AC Parker… - Proceedings of the …, 1990 - ieeexplore.ieee.org
High-level synthesis systems start with an abstract behavioral specification of a digital
system and find a register-transfer level structure that realizes the given behavior. The …

A formal approach to the scheduling problem in high level synthesis

CT Hwang, JH Lee, YC Hsu - IEEE Transactions on Computer …, 1991 - ieeexplore.ieee.org
An integer linear programming (ILP) model for the scheduling problem in high-level
synthesis is presented. In addition to time-constrained scheduling and resource-constrained …

Force-directed scheduling in automatic data path synthesis

PG Paulin, JP Knight - Proceedings of the 24th ACM/IEEE Design …, 1987 - dl.acm.org
The HAL system performs data path synthesis using a new scheduling algorithm that is part
of an interdependent scheduling and allocation scheme. This scheme uses an estimate of …

Data path allocation based on bipartite weighted matching

CY Huang, YS Chen, YL Lin, YC Hsu - … of the 27th ACM/IEEE Design …, 1991 - dl.acm.org
We propose a graph-theoretic approach for the data path allocation problem. We
decompose the problem into three subproblems:(1) register allocation,(2) operation …

[KNIHA][B] Processor description languages

P Mishra, N Dutt - 2011 - books.google.com
Efficient design of embedded processors plays a critical role in embedded systems design.
Processor description languages and their associated specification, exploration and rapid …

A dynamic and reliability-driven scheduling algorithm for parallel real-time jobs executing on heterogeneous clusters

X Qin, H Jiang - Journal of Parallel and Distributed Computing, 2005 - Elsevier
In this paper, a heuristic dynamic scheduling scheme for parallel real-time jobs executing on
a heterogeneous cluster is presented. In our system model, parallel real-time jobs, which are …

On the design of fault-tolerant scheduling strategies using primary-backup approach for computational grids with low replication costs

Q Zheng, B Veeravalli, CK Tham - IEEE Transactions on …, 2008 - ieeexplore.ieee.org
Fault-tolerant scheduling is an imperative step for large-scale computational grid systems,
as often geographically distributed nodes co-operate to execute a task. By and large …

Retargetable code generation based on structural processor description

R Leupers, P Marwedel - Design Automation for Embedded Systems, 1998 - Springer
Abstract Design automation for embedded systems comprising both hardware and software
components demands for code generators integrated into electronic CAD systems. These …