Turnitin
降AI改写
早检测系统
早降重系统
Turnitin-UK版
万方检测-期刊版
维普编辑部版
Grammarly检测
Paperpass检测
checkpass检测
PaperYY检测
Fault simulation and emulation tools to augment radiation-hardness assurance testing
As of 2013, the gold standard for assessing radiation-hardness assurance (RHA) for a
system, subsystem, or a component is accelerated radiation testing and/or pulsed laser …
system, subsystem, or a component is accelerated radiation testing and/or pulsed laser …
Layout-based modeling and mitigation of multiple event transients
Radiation-induced multiple event transients (METs) are expected to become more frequent
than single event transients (SETs) at nanoscale CMOS technology nodes. In this paper, a …
than single event transients (SETs) at nanoscale CMOS technology nodes. In this paper, a …
A novel layout-based single event transient injection approach to evaluate the soft error rate of large combinational circuits in complimentary metal-oxide …
Y Du, S Chen - IEEE Transactions on Reliability, 2015 - ieeexplore.ieee.org
As the technology scales down, space radiation induced soft errors are becoming a critical
issue for the reliability of Integrated Circuits (ICs). In this paper, we propose a novel layout …
issue for the reliability of Integrated Circuits (ICs). In this paper, we propose a novel layout …
A layout-based soft error vulnerability estimation approach for combinational circuits considering single event multiple transients (SEMTs)
X Cao, L **ao, J Li, R Zhang, S Liu… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
Radiation-induced single event transients (SETs) are expected to evolve to single event
multiple transients (SEMTs) due to the downscaling of transistor feature size, which also …
multiple transients (SEMTs) due to the downscaling of transistor feature size, which also …
Soft error reliability evaluation of nanoscale logic circuits in the presence of multiple transient faults
S Cai, B He, W Wang, P Liu, F Yu, L Yin, B Li… - Journal of Electronic …, 2020 - Springer
Radiation-induced single transient faults (STFs) are expected to evolve into multiple
transient faults (MTFs) at nanoscale CMOS technology nodes. For this reason, the reliability …
transient faults (MTFs) at nanoscale CMOS technology nodes. For this reason, the reliability …
Constrained placement methodology for reducing SER under single-event-induced charge sharing effects
This paper presents a methodology to reduce the impact of double faults in a circuit by
constraining the placement of its standard cells. A fault-injection emulation platform is used …
constraining the placement of its standard cells. A fault-injection emulation platform is used …
Alternative standard cell placement strategies for single-event multiple-transient mitigation
As fabrication technology scales towards smaller transistor sizes, lower critical charge, and
higher operating frequencies, single-event radiation effects are more likely to cause errant …
higher operating frequencies, single-event radiation effects are more likely to cause errant …
A hardware-software approach for on-line soft error mitigation in interrupt-driven applications
Integrity assurance of configuration data has a significant impact on microcontroller-based
systems reliability. This is especially true when running applications driven by events which …
systems reliability. This is especially true when running applications driven by events which …
A constrained layout placement approach to enhance pulse quenching effect in large combinational circuits
Y Du, S Chen, B Liu - IEEE Transactions on Device and …, 2013 - ieeexplore.ieee.org
A novel constrained layout placement approach is proposed to enhance the pulse
quenching effect in combinational circuits. This constrained algorithm can enlarge the …
quenching effect in combinational circuits. This constrained algorithm can enlarge the …
Impact of complex logic cell layout on the single-event transient sensitivity
YQ Aguiar, F Wrobel, JL Autran… - … on Nuclear Science, 2019 - ieeexplore.ieee.org
The design methodology based on standard cells is widely used in a broad range of very-
large-scale integration (VLSI) applications. Furthermore, several optimization algorithms can …
large-scale integration (VLSI) applications. Furthermore, several optimization algorithms can …