The power of priority: NoC based distributed cache coherency
The paper introduces network-on-chip (NoC) design methodology and low cost mechanisms
for supporting efficient cache access and cache coherency in future high-performance chip …
for supporting efficient cache access and cache coherency in future high-performance chip …
Energy-efficient hardware-accelerated synchronization for shared-L1-memory multiprocessor clusters
The steeply growing performance demands for highly power-and energy-constrained
processing systems such as end-nodes of the Internet-of-Things (IoT) have led to parallel …
processing systems such as end-nodes of the Internet-of-Things (IoT) have led to parallel …
Efficiency and scalability of barrier synchronization on noc based many-core architectures
Interconnects based on Networks-on-Chip are an appealing solution to address future
microprocessor designs where, very likely, hundreds of cores will be connected on a single …
microprocessor designs where, very likely, hundreds of cores will be connected on a single …
Time synchronization between EtherCAT network and external processor
SM Park, Y Kwon, JY Choi - IEEE Communications Letters, 2020 - ieeexplore.ieee.org
We employ an external processor to distribute the master computing load in the EtherCAT
networked control system and develop a method for time synchronization between the Linux …
networked control system and develop a method for time synchronization between the Linux …
Maximizing common idle time on multicore processors with shared memory
Nowadays, memory energy reduction attracts significant attention as main memory
consumes large amount of energy among all the energy consuming components. This paper …
consumes large amount of energy among all the energy consuming components. This paper …
Performance measurements of synchronization mechanisms on 16PE NoC based multi-core with dedicated synchronization and data NoC
G Tian, O Hammami - 2009 16th IEEE International Conference …, 2009 - ieeexplore.ieee.org
Multi-Processors System on Chip (MPSOC) are emerging as solutions for high performance
embedded systems. Although important work have been achieved in the design and …
embedded systems. Although important work have been achieved in the design and …
Notifying Memories for Dataflow Applications on Shared-Memory Parallel Computer
A Ghasemi - 2022 - theses.hal.science
Symmetric Shared-memory multiprocessor~(SMP) is the most widely used implementation
of high-performance multi-core processors. It offers a uniform shared memory view that …
of high-performance multi-core processors. It offers a uniform shared memory view that …
Hardware-accelerated energy-efficient synchronization and communication for ultra-low-power tightly coupled clusters
F Glaser, G Haugou, D Rossi… - … Design, Automation & …, 2019 - ieeexplore.ieee.org
Parallel ultra low power computing is emerging as an enabler to meet the growing
performance and energy efficiency demands in deeply embedded systems such as the end …
performance and energy efficiency demands in deeply embedded systems such as the end …
Lock spin wait operation for multi-threaded applications in a multi-core computing environment
MC Chiang, KV Vu - US Patent 9,378,069, 2016 - Google Patents
Multiprocessor System 304 a lock. The spin-waiting threads are then allocated a lock
response time that is less than the default lock response time of the operating system (OS) …
response time that is less than the default lock response time of the operating system (OS) …