(Continued) Primary Examiner—William Coleman (57) ABSTRACT An embodiment of a
semiconductor device includes a semi conductor substrate that includes a channel, a first …

High-electron-mobility transistor (HEMT) devices are described in this patent application. In
some implementa tions, the HEMT devices can include a back barrier hole injection …

An embodiment of a semiconductor device includes a semi conductor substrate that
includes an upper surface and a semiconductor layer, a first dielectric layer disposed over …

(57) ABSTRACT A semiconductor device includes a substrate, a III-nitride buffer layer on the
substrate, an N-channel transistor includ inga III-nitride N-channel layer on one portion of …

An apparatus includes a substrate. The apparatus further includes a group III-nitride buffer
layer on the substrate; a group III-nitride barrier layer on the group III-nitride buffer layer, the …

(57) ABSTRACT CMOS circuits may formed using p-channel gallium nitride transistors and n-
channel gallium nitride transistors, wherein both the p-channel gallium nitride transistors …

Described herein are methods and structures integrating one or more TMDC crystal
heteroepitaxially grown on one or more group III-Nitride (III-N) crystal. The TMDC crystal may …

Methods are provided for fabricating a HEMT (high-electron-mobility transistor) that involve
sequential epitaxial growth of III-nitride channel and barrier layers, followed by epitaxial …

(57) ABSTRACT A semiconductor device includes a substrate, a back-barrier layer arranged
on the substrate, the back-barrier layer including first p-type dopant atoms, an intermediate …

BACKGROUND 0001 Technical Field 0002 The present disclosure relates to a normally-off
transistor with reduced ON-state resistance and to a method for manufacturing the transistor …