An analysis of persistent memory use with WHISPER
Emerging non-volatile memory (NVM) technologies promise durability with read and write
latencies comparable to volatile memory (DRAM). We define Persistent Memory (PM) as …
latencies comparable to volatile memory (DRAM). We define Persistent Memory (PM) as …
{Prime+ Abort}: A {Timer-Free}{High-Precision} L3 Cache Attack using Intel {TSX}
Last-Level Cache (LLC) attacks typically exploit timing side channels in hardware, and thus
rely heavily on timers for their operation. Many proposed defenses against such side …
rely heavily on timers for their operation. Many proposed defenses against such side …
Software transactional memory: Why is it only a research toy?
Software transactional memory: why is it only a research toy? Page 1 40 communications of the
acm | NovEmbER 2008 | vol. 51 | No. 11 practice trAnsActionAL MEMorY (TM)13 is a …
acm | NovEmbER 2008 | vol. 51 | No. 11 practice trAnsActionAL MEMorY (TM)13 is a …
Early experience with a commercial hardware transactional memory implementation
We report on our experience with the hardware transactional memory (HTM) feature of two
pre-production revisions of a new commercial multicore processor. Our experience includes …
pre-production revisions of a new commercial multicore processor. Our experience includes …
An effective hybrid transactional memory system with strong isolation guarantees
We propose signature-accelerated transactional memory (SigTM), ahybrid TM system that
reduces the overhead of software transactions. SigTM uses hardware signatures to track the …
reduces the overhead of software transactions. SigTM uses hardware signatures to track the …
Performance pathologies in hardware transactional memory
Hardware Transactional Memory (HTM) systems reflect choices from three key design
dimensions: conflict detection, version management, and conflict resolution. Previously …
dimensions: conflict detection, version management, and conflict resolution. Previously …
Adaptive transaction scheduling for transactional memory systems
Transactional memory systems are expected to enable parallel programming at lower
programming complexity, while delivering improved performance over traditional lock-based …
programming complexity, while delivering improved performance over traditional lock-based …
PowerPi: Measuring and modeling the power consumption of the Raspberry Pi
F Kaup, P Gottschling… - 39th Annual IEEE …, 2014 - ieeexplore.ieee.org
An increasing number of households is connected to the Internet via DSL or cable, for which
home gateways are required. The optimization of these-caused by their large number-is a …
home gateways are required. The optimization of these-caused by their large number-is a …
A scalable architecture for ordered parallelism
We present Swarm, a novel architecture that exploits ordered irregular parallelism, which is
abundant but hard to mine with current software and hardware techniques. In this …
abundant but hard to mine with current software and hardware techniques. In this …
Evaluation of AMD's advanced synchronization facility within a complete transactional memory stack
AMD's Advanced Synchronization Facility (ASF) is an x86 instruction set extension proposal
intended to simplify and speed up the synchronization of concurrent programs. In this paper …
intended to simplify and speed up the synchronization of concurrent programs. In this paper …