The complexity of Networks-on-Chip (NoC) makes the application of traditional test methods
obsolete. For NoC, a combination of methods known from the System-on-Chip, memory and …

The study proposes a new concept of test and diagnosis in regular mesh-like network-on-a-
chip (NoC) designs. The method is based on functional fault models and it implements …

The paper presents a new structural fault-independent fault collapsing method based on the
topology analysis of the circuit, which has linear complexity. The minimal necessary set of …

BDDs have become the state-of-the-art data structure in VLSI CAD. In this paper, a special
class of BDDs is presented called Structurally Synthesized BDDs (SSBDD). The idea of …

The paper proposes a novel method of analyzing code coverage metrics on a system
representation called high-level decision diagrams (HLDD). Previous works have shown …

In this paper we give a short overview of the decision diagrams, and define a special class of
high-level decision diagrams (HLDD) for formal representation of digital systems. We show …

In this paper we present two methods for synthesis of high-level decision diagrams (HLDD)
for representing digital systems at higher behavior, functional or register-transfer levels. The …

This paper offers an Internet-based environment for enhancing problem-specific design
flows with test pattern generation and fault simulation capabilities. Automatic Test Pattern …

In order to cope with the complexity of today's digital systems in diagnostic modeling,
hierarchical multi-level approaches should be used. In this chapter, the possibilities of using …

The paper proposes a novel method for PSL language assertions simulation-based
checking. The method uses a system representation model called High-level decision …