A survey on deep learning hardware accelerators for heterogeneous hpc platforms

C Silvano, D Ielmini, F Ferrandi, L Fiorin… - arxiv preprint arxiv …, 2023 - arxiv.org
Recent trends in deep learning (DL) imposed hardware accelerators as the most viable
solution for several classes of high-performance computing (HPC) applications such as …

Reducing datacenter compute carbon footprint by harnessing the power of specialization: Principles, metrics, challenges and opportunities

T Eilam, P Bose, LP Carloni, A Cidon… - IEEE Transactions …, 2024 - ieeexplore.ieee.org
Computing is an indispensable tool in addressing climate change, but it also contributes to a
significant and steadily increasing carbon footprint, partly due to the exponential growth in …

Berry: Bit error robustness for energy-efficient reinforcement learning-based autonomous systems

Z Wan, N Chandramoorthy… - 2023 60th ACM/IEEE …, 2023 - ieeexplore.ieee.org
Autonomous systems, such as Unmanned Aerial Vehicles (UAVs), are expected to run
complex reinforcement learning (RL) models to execute fully autonomous position …

A heterogeneous risc-v based soc for secure nano-uav navigation

L Valente, A Nadalini, AHC Veeran… - … on Circuits and …, 2024 - ieeexplore.ieee.org
The rapid advancement of energy-efficient parallel ultra-low-power (ULP) controllers units
(MCUs) is enabling the development of autonomous nano-sized unmanned aerial vehicles …

FlooNoC: A 645-Gb/s/link 0.15-pJ/B/hop Open-Source NoC With Wide Physical Links and End-to-End AXI4 Parallel Multistream Support

T Fischer, M Rogenmoser, T Benz… - … Transactions on Very …, 2025 - ieeexplore.ieee.org
The new generation of domain-specific AI accelerators is characterized by rapidly increasing
demands for bulk data transfers, as opposed to small, latency-critical cache line transfers …

A scalable methodology for agile chip development with open-source hardware components

MC Santos, T Jia, M Cochet, K Swaminathan… - Proceedings of the 41st …, 2022 - dl.acm.org
We present a scalable methodology for the agile physical design of tile-based
heterogeneous system-on-chip (SoC) architectures that simplifies the reuse and integration …

BlitzCoin: Fully Decentralized hardware power management for accelerator-rich SoCs

M Cochet, K Swaminathan, E Loscalzo… - 2024 ACM/IEEE 51st …, 2024 - ieeexplore.ieee.org
On-chip power-management techniques have evolved over several processor generations.
However, response time and scalability constraints have made it difficult to translate existing …

Enabling heterogeneous, multicore soc research with RISC-V and ESP

J Zuckerman, P Mantovani, D Giri… - arxiv preprint arxiv …, 2022 - arxiv.org
Heterogeneous, multicore SoC architectures are a critical component of today's computing
landscape. However, supporting both increasing heterogeneity and multicore execution are …

Mozart: Taming taxes and composing accelerators with shared-memory

V Suresh, B Mishra, Y **g, Z Zhu, N **… - Proceedings of the …, 2024 - dl.acm.org
Resource-constrained system-on-chips (SoCs) are increasingly heterogeneous with
specialized accelerators for various tasks. Acceleration taxes due to control and data …

FlooNoC: A multi-Tb/s wide NoC for heterogeneous AXI4 traffic

T Fischer, M Rogenmoser, M Cavalcante… - IEEE Design & …, 2023 - ieeexplore.ieee.org
This article introduces an open-source, low-latency Network-on-Chip (NoC) designed to
tackle bandwidth challenges faced by traditional narrow and serialized NoCs. The authors …