Reconfigurable packet processing pipelines have emerged as a common building block for
offloading fast and efficient packet processing to programmable switches and SmartNICs …

In chip resource allocation, assigning blocks into a set of available stages in packet-
processing pipeline is a critical problem that will greatly influence the efficiency of chip …

Historically, network devices were mostly fixed-function ones. They could run at a line rate of
one network packet per nanosecond, but it was impossible to support newly developed …