Rapid progress in CMOS technology since the late 1990s has increased the vulnerability of
processors toward faults. Subsequently, the focus of computer architects has shifted toward …

Recent trends of aggressive technology scaling have greatly exacerbated the occurrences
and impact of faults in computing systems. This has madereliability'a first-order design …

Energy harvesting system has huge potential to enable battery-less Internet of Things (IoT)
services. However, it has been designed without a cache due to the difficulty of crash …

Read and write requests from a processor contend for the main memory data bus. System
performance depends heavily on when read requests are serviced since they are required …

This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of
providing error correction for SRAM caches. It is important to limit such overheads as …

Nonvolatile memory (NVM) technologies have gained increasing attention thanks to their
density and durability benefits. However, leveraging NVM can cause a crash consistency …

This paper presents PPA (Persistent Processor Architecture), simple microarchitectural
support for lightweight yet performant whole-system persistence. PPA offers fully transparent …

A compilation technique for reliability-aware software transformations is presented. An
instruction-level reliability estimation technique quantifies the effects of hardware-level faults …

Constraint multiset grammars provide a general, high-level framework for the definition of
visual languages. They are a new formalism based on multiset rewriting. We give a formal …

A gate-level probabilistic error propagation model is presented which takes as input the
Boolean function of the gate, input signal probabilities, the error probability at the gate …